src/cpu/inorder/resource.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_HH__
  33 #define __CPU_INORDER_RESOURCE_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/sim_object.hh"
  44
  45 class Event;
  46 class InOrderCPU;
  47 class ResourceEvent;
  48 class ResourceRequest;
  49
  50 typedef ResourceRequest ResReq;
  51 typedef ResourceRequest* ResReqPtr;
  52
  53 class Resource {
  54   public:
  55     typedef ThePipeline::DynInstPtr DynInstPtr;
  56
  57     friend class ResourceEvent;
  58     friend class ResourceRequest;
  59
  60   public:
  61     Resource(std::string res_name, int res_id, int res_width,
  62              int res_latency, InOrderCPU *_cpu);
  63     virtual ~Resource();
  64
  65
  66     /** Return name of this resource */
  67     virtual std::string name();
  68
  69     /** Define this function if resource, has a port to connect to an outside
  70      *  simulation object.
  71      */
  72     virtual Port* getPort(const std::string &if_name, int idx) { return NULL; }
  73
  74     /** Return ID for this resource */
  75     int getId() { return id; }
  76
  77     /** Any extra initiliazation stuff can be set up using this function that
  78      * should get called before the simulation starts (tick 0)
  79      */
  80     virtual void init();
  81     virtual void initSlots();
  82
  83     /** Register Stats for this resource */
  84     virtual void regStats();
  85
  86     /** Resources that care about thread activation override this. */
  87     virtual void activateThread(ThreadID tid) { }
  88
  89     /** Deactivate Thread. Default action is to squash all instructions
  90      *  from deactivated thread.
  91      */
  92     virtual void deactivateThread(ThreadID tid);
  93
  94     /** Resources that care when an instruction has been graduated
  95      *  can override this
  96      */
  97     virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
  98
  99     /** Request usage of this resource. Returns a ResourceRequest object
 100      *  with all the necessary resource information
 101      */
 102     virtual ResourceRequest* request(DynInstPtr inst);
 103
 104     /** Get the next available slot in this resource. Instruction is passed
 105      *  so that resources can check the instruction before allocating a slot
 106      *  if necessary.
 107      */
 108     virtual int getSlot(DynInstPtr inst);
 109
 110     /** Find the slot that this instruction is using in a resource */
 111     virtual int findSlot(DynInstPtr inst);
 112
 113     /** Free a resource slot */
 114     virtual void freeSlot(int slot_idx);
 115
 116     /** Request usage of a resource for this instruction. If this instruction already
 117      *  has made this request to this resource, and that request is uncompleted
 118      *  this function will just return that request
 119      */
 120     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 121                                         int res_idx, int slot_num,
 122                                         unsigned cmd);
 123
 124     /** Schedule Execution of This Resource For A Given Slot*/
 125     virtual void scheduleExecution(int slot_idx);
 126
 127     /** Execute the function of this resource. The Default is action
 128      *  is to do nothing. More specific models will derive from this
 129      *  class and define their own execute function.
 130      */
 131     virtual void execute(int slot_idx);
 132
 133     /** Fetch on behalf of an instruction. Will check to see
 134      *  if instruction is actually in resource before
 135      *  trying to fetch. Needs to be defined for derived units.
 136      */
 137     virtual Fault doFetchAccess(DynInstPtr inst)
 138     { panic("doFetchAccess undefined for %s", name()); return NoFault; }
 139
 140     /** Read/Write on behalf of an instruction. Will check to see
 141      *  if instruction is actually in resource before
 142      *  trying to do access.Needs to be defined for derived units.
 143      */
 144     virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
 145     { panic("doCacheAccess undefined for %s", name()); return NoFault; }
 146
 147     virtual void prefetch(DynInstPtr inst)
 148     { panic("prefetch undefined for %s", name()); }
 149
 150     virtual void writeHint(DynInstPtr inst)
 151     { panic("writeHint undefined for %s", name()); }
 152
 153     /** Squash All Requests After This Seq Num */
 154     virtual void squash(DynInstPtr inst, int stage_num,
 155                         InstSeqNum squash_seq_num, ThreadID tid);
 156
 157     /** The number of instructions available that this resource can
 158      *  can still process
 159      */
 160     int slotsAvail();
 161
 162     /** The number of instructions using this resource */
 163     int slotsInUse();
 164
 165     /** Schedule resource event, regardless of its current state. */
 166     void scheduleEvent(int slot_idx, int delay);
 167
 168     /** Find instruction in list, Schedule resource event, regardless of its current state. */
 169     bool scheduleEvent(DynInstPtr inst, int delay);
 170
 171     /** Unschedule resource event, regardless of its current state. */
 172     void unscheduleEvent(int slot_idx);
 173
 174     /** Unschedule resource event, regardless of its current state. */
 175     bool unscheduleEvent(DynInstPtr inst);
 176
 177     /** Return the number of cycles in 'Tick' format */
 178     Tick ticks(int numCycles);
 179
 180     /** Find the request that corresponds to this instruction */
 181     virtual ResReqPtr findRequest(DynInstPtr inst);
 182
 183     /** */
 184     virtual void rejectRequest(DynInstPtr inst);
 185
 186     /** Request a Resource again. Some resources have to special process this
 187      *  in subsequent accesses.
 188      */
 189     virtual void requestAgain(DynInstPtr inst, bool &try_request);
 190
 191     /** Return Latency of Resource */
 192     /*  Can be overridden for complex cases */
 193     virtual int getLatency(int slot_num) { return latency; }
 194
 195   protected:
 196     /** The name of this resource */
 197     std::string resName;
 198
 199     /** ID of the resource. The Resource Pool uses this # to identify this
 200      *  resource.
 201      */
 202     int id;
 203
 204     /** The number of instructions the resource can simultaneously
 205      *  process.
 206      */
 207     int width;
 208
 209     /** Constant latency for this resource.
 210      *  Note: Dynamic latency resources set this to 0 and
 211      *  manage the latency themselves
 212      */
 213     const int latency;
 214
 215   public:
 216     /** Mapping of slot-numbers to the resource-request pointers */
 217     std::map<int, ResReqPtr> reqMap;
 218
 219     /** A list of all the available execution slots for this resource.
 220      *  This correlates with the actual resource event idx.
 221      */
 222     std::vector<int> availSlots;
 223
 224     /** The CPU(s) that this resource interacts with */
 225     InOrderCPU *cpu;
 226
 227   protected:
 228     /** The resource event used for scheduling resource slots on the
 229      *  event queue
 230      */
 231     ResourceEvent *resourceEvent;
 232
 233     /** Default denied resource request pointer*/
 234     ResReqPtr deniedReq;
 235
 236   public:
 237     /////////////////////////////////////////////////////////////////
 238     //
 239     // DEFAULT RESOURCE STATISTICS
 240     //
 241     /////////////////////////////////////////////////////////////////
 242     /** Number of Instruction Requests the Resource Processes */
 243     Stats::Scalar instReqsProcessed;
 244 };
 245
 246 class ResourceEvent : public Event
 247 {
 248   public:
 249     /** Pointer to the CPU. */
 250     Resource *resource;
 251
 252
 253     /// Resource events that come before other associated CPU events
 254     /// (for InOrderCPU model).
 255     /// check src/sim/eventq.hh for more event priorities.
 256     enum InOrderPriority {
 257         Resource_Event_Pri      =   45,
 258     };
 259
 260     /** The Resource Slot that this event is servicing */
 261     int slotIdx;
 262
 263     /** Constructs a resource event. */
 264     ResourceEvent();
 265     ResourceEvent(Resource *res, int slot_idx);
 266     virtual ~ResourceEvent() { }
 267
 268     /** Initialize data for this resource event. */
 269     virtual void init(Resource *res, int slot_idx);
 270
 271     /** Processes a resource event. */
 272     virtual void process();
 273
 274     /** Returns the description of the resource event. */
 275     const char *description();
 276
 277     /** Set slot idx for event */
 278     void setSlot(int slot) { slotIdx = slot; }
 279
 280     /** Schedule resource event, regardless of its current state. */
 281     void scheduleEvent(int delay)
 282     {
 283         if (squashed())
 284           mainEventQueue.reschedule(this, curTick + resource->ticks(delay));
 285         else if (!scheduled())
 286           mainEventQueue.schedule(this, curTick + resource->ticks(delay));
 287     }
 288
 289     /** Unschedule resource event, regardless of its current state. */
 290     void unscheduleEvent()
 291     {
 292         if (scheduled())
 293             squash();
 294     }
 295
 296 };
 297
 298 class ResourceRequest
 299 {
 300   public:
 301     typedef ThePipeline::DynInstPtr DynInstPtr;
 302
 303     static int resReqID;
 304
 305     static int resReqCount;
 306
 307   public:
 308     ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
 309                     int res_idx, int slot_num, unsigned _cmd)
 310         : res(_res), inst(_inst), cmd(_cmd),  stageNum(stage_num),
 311           resIdx(res_idx), slotNum(slot_num), completed(false),
 312           squashed(false), processing(false), waiting(false)
 313     {
 314         reqID = resReqID++;
 315         resReqCount++;
 316         DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID, resReqCount);
 317
 318         if (resReqCount > 100) {
 319             fatal("Too many undeleted resource requests. Memory leak?\n");
 320         }
 321     }
 322
 323     virtual ~ResourceRequest()
 324     {
 325         resReqCount--;
 326         DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID, resReqCount);
 327     }
 328
 329     int reqID;
 330
 331     /** Acknowledge that this is a request is done and remove
 332      *  from resource.
 333      */
 334     void done(bool completed = true);
 335
 336     /////////////////////////////////////////////
 337     //
 338     // GET RESOURCE REQUEST IDENTIFICATION / INFO
 339     //
 340     /////////////////////////////////////////////
 341     /** Get Resource Index */
 342     int getResIdx() { return resIdx; }
 343
 344     /** Get Slot Number */
 345     int getSlot() { return slotNum; }
 346
 347     /** Get Stage Number */
 348     int getStageNum() { return stageNum; }
 349
 350     /** Set/Get Thread Ids */
 351     void setTid(ThreadID _tid) { tid = _tid; }
 352     ThreadID getTid() { return tid; }
 353
 354     /** Instruction this request is for */
 355     DynInstPtr getInst() { return inst; }
 356
 357     /** Data from this request. Overridden by Resource-Specific Request
 358      *  Objects
 359      */
 360     virtual PacketDataPtr getData() { return NULL; }
 361
 362     /** Pointer to Resource that is being used */
 363     Resource *res;
 364
 365     /** Instruction being used */
 366     DynInstPtr inst;
 367
 368     /** Fault Associated With This Resource Request */
 369     Fault fault;
 370
 371     /** Command For This Resource */
 372     unsigned cmd;
 373
 374     ////////////////////////////////////////
 375     //
 376     // GET RESOURCE REQUEST STATUS FROM VARIABLES
 377     //
 378     ////////////////////////////////////////
 379     /** Get/Set Completed variables */
 380     bool isCompleted() { return completed; }
 381     void setCompleted(bool cond = true) { completed = cond; }
 382
 383     /** Get/Set Squashed variables */
 384     bool isSquashed() { return squashed; }
 385     void setSquashed() { squashed = true; }
 386
 387     /** Get/Set IsProcessing variables */
 388     bool isProcessing() { return processing; }
 389     void setProcessing() { processing = true; }
 390
 391     /** Get/Set IsWaiting variables */
 392     bool isWaiting() { return waiting; }
 393     void setWaiting() { waiting = true; }
 394
 395   protected:
 396     /** Resource Identification */
 397     ThreadID tid;
 398     int stageNum;
 399     int resIdx;
 400     int slotNum;
 401
 402     /** Resource Status */
 403     bool completed;
 404     bool squashed;
 405     bool processing;
 406     bool waiting;
 407 };
 408
 409 #endif //__CPU_INORDER_RESOURCE_HH__