src/cpu/inorder/resource.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_HH__
  33 #define __CPU_INORDER_RESOURCE_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/sim_object.hh"
  44
  45 class Event;
  46 class InOrderCPU;
  47 class ResourceEvent;
  48 class ResourceRequest;
  49
  50 typedef ResourceRequest ResReq;
  51 typedef ResourceRequest* ResReqPtr;
  52
  53 class Resource {
  54   public:
  55     typedef ThePipeline::DynInstPtr DynInstPtr;
  56
  57     friend class ResourceEvent;
  58     friend class ResourceRequest;
  59
  60   public:
  61     Resource(std::string res_name, int res_id, int res_width,
  62              int res_latency, InOrderCPU *_cpu);
  63     virtual ~Resource() {}
  64
  65     /** Return name of this resource */
  66     virtual std::string name();
  67
  68     /** Define this function if resource, has a port to connect to an outside
  69      *  simulation object.
  70      */
  71     virtual Port* getPort(const std::string &if_name, int idx) { return NULL; }
  72
  73     /** Return ID for this resource */
  74     int getId() { return id; }
  75
  76     /** Any extra initiliazation stuff can be set up using this function that
  77      * should get called before the simulation starts (tick 0)
  78      */
  79     virtual void init();
  80     virtual void initSlots();
  81
  82     /** Register Stats for this resource */
  83     virtual void regStats();
  84
  85     /** Resources that care about thread activation override this. */
  86     virtual void activateThread(unsigned tid) { }
  87
  88     /** Deactivate Thread. Default action is to squash all instructions
  89      *  from deactivated thread.
  90      */
  91     virtual void deactivateThread(unsigned tid);
  92
  93     /** Resources that care when an instruction has been graduated
  94      *  can override this
  95      */
  96     virtual void instGraduated(InstSeqNum seq_num,unsigned tid) { }
  97
  98     /** Request usage of this resource. Returns a ResourceRequest object
  99      *  with all the necessary resource information
 100      */
 101     virtual ResourceRequest* request(DynInstPtr inst);
 102
 103     /** Get the next available slot in this resource. Instruction is passed
 104      *  so that resources can check the instruction before allocating a slot
 105      *  if necessary.
 106      */
 107     virtual int getSlot(DynInstPtr inst);
 108
 109     /** Find the slot that this instruction is using in a resource */
 110     virtual int findSlot(DynInstPtr inst);
 111
 112     /** Free a resource slot */
 113     virtual void freeSlot(int slot_idx);
 114
 115     /** Request usage of a resource for this instruction. If this instruction already
 116      *  has made this request to this resource, and that request is uncompleted
 117      *  this function will just return that request
 118      */
 119     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 120                                         int res_idx, int slot_num,
 121                                         unsigned cmd);
 122
 123     /** Schedule Execution of This Resource For A Given Slot*/
 124     virtual void scheduleExecution(int slot_idx);
 125
 126     /** Execute the function of this resource. The Default is action
 127      *  is to do nothing. More specific models will derive from this
 128      *  class and define their own execute function.
 129      */
 130     virtual void execute(int slot_idx);
 131
 132     /** Fetch on behalf of an instruction. Will check to see
 133      *  if instruction is actually in resource before
 134      *  trying to fetch. Needs to be defined for derived units.
 135      */
 136     virtual Fault doFetchAccess(DynInstPtr inst)
 137     { panic("doFetchAccess undefined for %s", name()); return NoFault; }
 138
 139     /** Read/Write on behalf of an instruction. Will check to see
 140      *  if instruction is actually in resource before
 141      *  trying to do access.Needs to be defined for derived units.
 142      */
 143     virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
 144     { panic("doCacheAccess undefined for %s", name()); return NoFault; }
 145
 146     virtual void prefetch(DynInstPtr inst)
 147     { panic("prefetch undefined for %s", name()); }
 148
 149     virtual void writeHint(DynInstPtr inst)
 150     { panic("writeHint undefined for %s", name()); }
 151
 152     /** Squash All Requests After This Seq Num */
 153     virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
 154
 155     /** The number of instructions available that this resource can
 156      *  can still process
 157      */
 158     int slotsAvail();
 159
 160     /** The number of instructions using this resource */
 161     int slotsInUse();
 162
 163     /** Schedule resource event, regardless of its current state. */
 164     void scheduleEvent(int slot_idx, int delay);
 165
 166     /** Find instruction in list, Schedule resource event, regardless of its current state. */
 167     bool scheduleEvent(DynInstPtr inst, int delay);
 168
 169     /** Unschedule resource event, regardless of its current state. */
 170     void unscheduleEvent(int slot_idx);
 171
 172     /** Unschedule resource event, regardless of its current state. */
 173     bool unscheduleEvent(DynInstPtr inst);
 174
 175     /** Return the number of cycles in 'Tick' format */
 176     Tick ticks(int numCycles);
 177
 178     /** Find the request that corresponds to this instruction */
 179     virtual ResReqPtr findRequest(DynInstPtr inst);
 180
 181     /** */
 182     virtual void rejectRequest(DynInstPtr inst);
 183
 184     /** Request a Resource again. Some resources have to special process this
 185      *  in subsequent accesses.
 186      */
 187     virtual void requestAgain(DynInstPtr inst, bool &try_request);
 188
 189     /** Return Latency of Resource */
 190     /*  Can be overridden for complex cases */
 191     virtual int getLatency(int slot_num) { return latency; }
 192
 193   protected:
 194     /** The name of this resource */
 195     std::string resName;
 196
 197     /** ID of the resource. The Resource Pool uses this # to identify this
 198      *  resource.
 199      */
 200     int id;
 201
 202     /** The number of instructions the resource can simultaneously
 203      *  process.
 204      */
 205     int width;
 206
 207     /** Constant latency for this resource.
 208      *  Note: Dynamic latency resources set this to 0 and
 209      *  manage the latency themselves
 210      */
 211     const int latency;
 212
 213   public:
 214     /** Mapping of slot-numbers to the resource-request pointers */
 215     std::map<int, ResReqPtr> reqMap;
 216
 217     /** A list of all the available execution slots for this resource.
 218      *  This correlates with the actual resource event idx.
 219      */
 220     std::vector<int> availSlots;
 221
 222     /** The CPU(s) that this resource interacts with */
 223     InOrderCPU *cpu;
 224
 225   protected:
 226     /** The resource event used for scheduling resource slots on the
 227      *  event queue
 228      */
 229     ResourceEvent *resourceEvent;
 230
 231     /** Default denied resource request pointer*/
 232     ResReqPtr deniedReq;
 233
 234   public:
 235     /////////////////////////////////////////////////////////////////
 236     //
 237     // DEFAULT RESOURCE STATISTICS
 238     //
 239     /////////////////////////////////////////////////////////////////
 240     /** Number of Instruction Requests the Resource Processes */
 241     Stats::Scalar instReqsProcessed;
 242 };
 243
 244 class ResourceEvent : public Event
 245 {
 246   public:
 247     /** Pointer to the CPU. */
 248     Resource *resource;
 249
 250
 251     /// Resource events that come before other associated CPU events
 252     /// (for InOrderCPU model).
 253     /// check src/sim/eventq.hh for more event priorities.
 254     enum InOrderPriority {
 255         Resource_Event_Pri      =   45,
 256     };
 257
 258     /** The Resource Slot that this event is servicing */
 259     int slotIdx;
 260
 261     /** Constructs a resource event. */
 262     ResourceEvent();
 263     ResourceEvent(Resource *res, int slot_idx);
 264     virtual ~ResourceEvent() { }
 265
 266     /** Initialize data for this resource event. */
 267     virtual void init(Resource *res, int slot_idx);
 268
 269     /** Processes a resource event. */
 270     virtual void process();
 271
 272     /** Returns the description of the resource event. */
 273     const char *description();
 274
 275     /** Set slot idx for event */
 276     void setSlot(int slot) { slotIdx = slot; }
 277
 278     /** Schedule resource event, regardless of its current state. */
 279     void scheduleEvent(int delay)
 280     {
 281         if (squashed())
 282           mainEventQueue.reschedule(this, curTick + resource->ticks(delay));
 283         else if (!scheduled())
 284           mainEventQueue.schedule(this, curTick + resource->ticks(delay));
 285     }
 286
 287     /** Unschedule resource event, regardless of its current state. */
 288     void unscheduleEvent()
 289     {
 290         if (scheduled())
 291             squash();
 292     }
 293
 294 };
 295
 296 class ResourceRequest
 297 {
 298   public:
 299     typedef ThePipeline::DynInstPtr DynInstPtr;
 300
 301     static int resReqID;
 302
 303     static int resReqCount;
 304
 305   public:
 306     ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
 307                     int res_idx, int slot_num, unsigned _cmd)
 308         : res(_res), inst(_inst), cmd(_cmd),  stageNum(stage_num),
 309           resIdx(res_idx), slotNum(slot_num), completed(false),
 310           squashed(false), processing(false), waiting(false)
 311     {
 312         reqID = resReqID++;
 313         resReqCount++;
 314         DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID, resReqCount);
 315
 316         if (resReqCount > 100) {
 317             fatal("Too many undeleted resource requests. Memory leak?\n");
 318         }
 319     }
 320
 321     virtual ~ResourceRequest()
 322     {
 323         resReqCount--;
 324         DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID, resReqCount);
 325     }
 326
 327     int reqID;
 328
 329     /** Acknowledge that this is a request is done and remove
 330      *  from resource.
 331      */
 332     void done(bool completed = true);
 333
 334     /////////////////////////////////////////////
 335     //
 336     // GET RESOURCE REQUEST IDENTIFICATION / INFO
 337     //
 338     /////////////////////////////////////////////
 339     /** Get Resource Index */
 340     int getResIdx() { return resIdx; }
 341
 342     /** Get Slot Number */
 343     int getSlot() { return slotNum; }
 344
 345     /** Get Stage Number */
 346     int getStageNum() { return stageNum; }
 347
 348     /** Set/Get Thread Ids */
 349     void setTid(unsigned _tid) { tid = _tid; }
 350     int getTid() { return tid; }
 351
 352     /** Instruction this request is for */
 353     DynInstPtr getInst() { return inst; }
 354
 355     /** Data from this request. Overridden by Resource-Specific Request
 356      *  Objects
 357      */
 358     virtual PacketDataPtr getData() { return NULL; }
 359
 360     /** Pointer to Resource that is being used */
 361     Resource *res;
 362
 363     /** Instruction being used */
 364     DynInstPtr inst;
 365
 366     /** Fault Associated With This Resource Request */
 367     Fault fault;
 368
 369     /** Command For This Resource */
 370     unsigned cmd;
 371
 372     ////////////////////////////////////////
 373     //
 374     // GET RESOURCE REQUEST STATUS FROM VARIABLES
 375     //
 376     ////////////////////////////////////////
 377     /** Get/Set Completed variables */
 378     bool isCompleted() { return completed; }
 379     void setCompleted(bool cond = true) { completed = cond; }
 380
 381     /** Get/Set Squashed variables */
 382     bool isSquashed() { return squashed; }
 383     void setSquashed() { squashed = true; }
 384
 385     /** Get/Set IsProcessing variables */
 386     bool isProcessing() { return processing; }
 387     void setProcessing() { processing = true; }
 388
 389     /** Get/Set IsWaiting variables */
 390     bool isWaiting() { return waiting; }
 391     void setWaiting() { waiting = true; }
 392
 393   protected:
 394     /** Resource Identification */
 395     int tid;
 396     int stageNum;
 397     int resIdx;
 398     int slotNum;
 399
 400     /** Resource Status */
 401     bool completed;
 402     bool squashed;
 403     bool processing;
 404     bool waiting;
 405 };
 406
 407 #endif //__CPU_INORDER_RESOURCE_HH__