src/cpu/inorder/resource.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_HH__
  33 #define __CPU_INORDER_RESOURCE_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/sim_object.hh"
  44
  45 class Event;
  46 class InOrderCPU;
  47 class ResourceEvent;
  48 class ResourceRequest;
  49
  50 typedef ResourceRequest ResReq;
  51 typedef ResourceRequest* ResReqPtr;
  52
  53 class Resource {
  54   public:
  55     typedef ThePipeline::DynInstPtr DynInstPtr;
  56
  57     friend class ResourceEvent;
  58     friend class ResourceRequest;
  59
  60   public:
  61     Resource(std::string res_name, int res_id, int res_width,
  62              int res_latency, InOrderCPU *_cpu);
  63     virtual ~Resource() {}
  64
  65     /** Return name of this resource */
  66     virtual std::string name();
  67
  68     /** Define this function if resource, has a port to connect to an outside
  69      *  simulation object.
  70      */
  71     virtual Port* getPort(const std::string &if_name, int idx) { return NULL; }
  72
  73     /** Return ID for this resource */
  74     int getId() { return id; }
  75
  76     /** Any extra initiliazation stuff can be set up using this function that
  77      * should get called before the simulation starts (tick 0)
  78      */
  79     virtual void init();
  80     virtual void initSlots();
  81
  82     /** Register Stats for this resource */
  83     virtual void regStats();
  84
  85     /** Resources that care about thread activation override this. */
  86     virtual void activateThread(unsigned tid) { }
  87
  88     /** Deactivate Thread. Default action is to squash all instructions
  89      *  from deactivated thread.
  90      */
  91     virtual void deactivateThread(unsigned tid);
  92
  93     /** Resources that care when an instruction has been graduated
  94      *  can override this
  95      */
  96     virtual void instGraduated(InstSeqNum seq_num,unsigned tid) { }
  97
  98     /** Request usage of this resource. Returns a ResourceRequest object
  99      *  with all the necessary resource information
 100      */
 101     virtual ResourceRequest* request(DynInstPtr inst);
 102
 103     /** Get the next available slot in this resource. Instruction is passed
 104      *  so that resources can check the instruction before allocating a slot
 105      *  if necessary.
 106      */
 107     virtual int getSlot(DynInstPtr inst);
 108
 109     /** Find the slot that this instruction is using in a resource */
 110     virtual int findSlot(DynInstPtr inst);
 111
 112     /** Free a resource slot */
 113     virtual void freeSlot(int slot_idx);
 114
 115     /** Request usage of a resource for this instruction. If this instruction already
 116      *  has made this request to this resource, and that request is uncompleted
 117      *  this function will just return that request
 118      */
 119     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 120                                         int res_idx, int slot_num,
 121                                         unsigned cmd);
 122
 123     /** Schedule Execution of This Resource For A Given Slot*/
 124     virtual void scheduleExecution(int slot_idx);
 125
 126     /** Execute the function of this resource. The Default is action
 127      *  is to do nothing. More specific models will derive from this
 128      *  class and define their own execute function.
 129      */
 130     virtual void execute(int slot_idx);
 131
 132     /** Fetch on behalf of an instruction. Will check to see
 133      *  if instruction is actually in resource before
 134      *  trying to fetch. Needs to be defined for derived units.
 135      */
 136     virtual Fault doFetchAccess(DynInstPtr inst)
 137     { panic("doFetchAccess undefined for %s", name()); return NoFault; }
 138
 139     /** Read/Write on behalf of an instruction. Will check to see
 140      *  if instruction is actually in resource before
 141      *  trying to do access.Needs to be defined for derived units.
 142      */
 143     virtual Fault doDataAccess(DynInstPtr inst, uint64_t *res=NULL)
 144     { panic("doDataAccess undefined for %s", name()); return NoFault; }
 145
 146     virtual void prefetch(DynInstPtr inst)
 147     { panic("prefetch undefined for %s", name()); }
 148
 149     virtual void writeHint(DynInstPtr inst)
 150     { panic("doDataAccess undefined for %s", name()); }
 151
 152
 153     /** Squash All Requests After This Seq Num */
 154     virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
 155
 156     /** The number of instructions available that this resource can
 157      *  can still process
 158      */
 159     int slotsAvail();
 160
 161     /** The number of instructions using this resource */
 162     int slotsInUse();
 163
 164     /** Schedule resource event, regardless of its current state. */
 165     void scheduleEvent(int slot_idx, int delay);
 166
 167     /** Find instruction in list, Schedule resource event, regardless of its current state. */
 168     bool scheduleEvent(DynInstPtr inst, int delay);
 169
 170     /** Unschedule resource event, regardless of its current state. */
 171     void unscheduleEvent(int slot_idx);
 172
 173     /** Unschedule resource event, regardless of its current state. */
 174     bool unscheduleEvent(DynInstPtr inst);
 175
 176     /** Return the number of cycles in 'Tick' format */
 177     Tick ticks(int numCycles);
 178
 179     /** Find the request that corresponds to this instruction */
 180     virtual ResReqPtr findRequest(DynInstPtr inst);
 181
 182     /** */
 183     virtual void rejectRequest(DynInstPtr inst);
 184
 185     /** Request a Resource again. Some resources have to special process this
 186      *  in subsequent accesses.
 187      */
 188     virtual void requestAgain(DynInstPtr inst, bool &try_request);
 189
 190     /** Return Latency of Resource */
 191     /*  Can be overridden for complex cases */
 192     virtual int getLatency(int slot_num) { return latency; }
 193
 194   protected:
 195     /** The name of this resource */
 196     std::string resName;
 197
 198     /** ID of the resource. The Resource Pool uses this # to identify this
 199      *  resource.
 200      */
 201     int id;
 202
 203     /** The number of instructions the resource can simultaneously
 204      *  process.
 205      */
 206     int width;
 207
 208     /** Constant latency for this resource.
 209      *  Note: Dynamic latency resources set this to 0 and
 210      *  manage the latency themselves
 211      */
 212     const int latency;
 213
 214   public:
 215     /** Mapping of slot-numbers to the resource-request pointers */
 216     std::map<int, ResReqPtr> reqMap;
 217
 218     /** A list of all the available execution slots for this resource.
 219      *  This correlates with the actual resource event idx.
 220      */
 221     std::vector<int> availSlots;
 222
 223     /** The CPU(s) that this resource interacts with */
 224     InOrderCPU *cpu;
 225
 226   protected:
 227     /** The resource event used for scheduling resource slots on the
 228      *  event queue
 229      */
 230     ResourceEvent *resourceEvent;
 231
 232     /** Default denied resource request pointer*/
 233     ResReqPtr deniedReq;
 234
 235   public:
 236     /////////////////////////////////////////////////////////////////
 237     //
 238     // DEFAULT RESOURCE STATISTICS
 239     //
 240     /////////////////////////////////////////////////////////////////
 241     /** Number of Instruction Requests the Resource Processes */
 242     Stats::Scalar instReqsProcessed;
 243 };
 244
 245 class ResourceEvent : public Event
 246 {
 247   public:
 248     /** Pointer to the CPU. */
 249     Resource *resource;
 250
 251
 252     /// Resource events that come before other associated CPU events
 253     /// (for InOrderCPU model).
 254     /// check src/sim/eventq.hh for more event priorities.
 255     enum InOrderPriority {
 256         Resource_Event_Pri      =   45,
 257     };
 258
 259     /** The Resource Slot that this event is servicing */
 260     int slotIdx;
 261
 262     /** Constructs a resource event. */
 263     ResourceEvent();
 264     ResourceEvent(Resource *res, int slot_idx);
 265     virtual ~ResourceEvent() { }
 266
 267     /** Initialize data for this resource event. */
 268     virtual void init(Resource *res, int slot_idx);
 269
 270     /** Processes a resource event. */
 271     virtual void process();
 272
 273     /** Returns the description of the resource event. */
 274     const char *description();
 275
 276     /** Set slot idx for event */
 277     void setSlot(int slot) { slotIdx = slot; }
 278
 279     /** Schedule resource event, regardless of its current state. */
 280     void scheduleEvent(int delay)
 281     {
 282         if (squashed())
 283           mainEventQueue.reschedule(this, curTick + resource->ticks(delay));
 284         else if (!scheduled())
 285           mainEventQueue.schedule(this, curTick + resource->ticks(delay));
 286     }
 287
 288     /** Unschedule resource event, regardless of its current state. */
 289     void unscheduleEvent()
 290     {
 291         if (scheduled())
 292             squash();
 293     }
 294
 295 };
 296
 297 class ResourceRequest
 298 {
 299   public:
 300     typedef ThePipeline::DynInstPtr DynInstPtr;
 301
 302     static int resReqID;
 303
 304     static int resReqCount;
 305
 306   public:
 307     ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
 308                     int res_idx, int slot_num, unsigned _cmd)
 309         : res(_res), inst(_inst), cmd(_cmd),  stageNum(stage_num),
 310           resIdx(res_idx), slotNum(slot_num), completed(false),
 311           squashed(false), processing(false), waiting(false)
 312     {
 313         reqID = resReqID++;
 314         resReqCount++;
 315         DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID, resReqCount);
 316
 317         if (resReqCount > 100) {
 318             fatal("Too many undeleted resource requests. Memory leak?\n");
 319         }
 320     }
 321
 322     virtual ~ResourceRequest()
 323     {
 324         resReqCount--;
 325         DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID, resReqCount);
 326     }
 327
 328     int reqID;
 329
 330     /** Acknowledge that this is a request is done and remove
 331      *  from resource.
 332      */
 333     void done(bool completed = true);
 334
 335     /////////////////////////////////////////////
 336     //
 337     // GET RESOURCE REQUEST IDENTIFICATION / INFO
 338     //
 339     /////////////////////////////////////////////
 340     /** Get Resource Index */
 341     int getResIdx() { return resIdx; }
 342
 343     /** Get Slot Number */
 344     int getSlot() { return slotNum; }
 345
 346     /** Get Stage Number */
 347     int getStageNum() { return stageNum; }
 348
 349     /** Set/Get Thread Ids */
 350     void setTid(unsigned _tid) { tid = _tid; }
 351     int getTid() { return tid; }
 352
 353     /** Instruction this request is for */
 354     DynInstPtr getInst() { return inst; }
 355
 356     /** Data from this request. Overridden by Resource-Specific Request
 357      *  Objects
 358      */
 359     virtual PacketDataPtr getData() { return NULL; }
 360
 361     /** Pointer to Resource that is being used */
 362     Resource *res;
 363
 364     /** Instruction being used */
 365     DynInstPtr inst;
 366
 367     /** Fault Associated With This Resource Request */
 368     Fault fault;
 369
 370     /** Command For This Resource */
 371     unsigned cmd;
 372
 373     ////////////////////////////////////////
 374     //
 375     // GET RESOURCE REQUEST STATUS FROM VARIABLES
 376     //
 377     ////////////////////////////////////////
 378     /** Get/Set Completed variables */
 379     bool isCompleted() { return completed; }
 380     void setCompleted(bool cond = true) { completed = cond; }
 381
 382     /** Get/Set Squashed variables */
 383     bool isSquashed() { return squashed; }
 384     void setSquashed() { squashed = true; }
 385
 386     /** Get/Set IsProcessing variables */
 387     bool isProcessing() { return processing; }
 388     void setProcessing() { processing = true; }
 389
 390     /** Get/Set IsWaiting variables */
 391     bool isWaiting() { return waiting; }
 392     void setWaiting() { waiting = true; }
 393
 394   protected:
 395     /** Resource Identification */
 396     int tid;
 397     int stageNum;
 398     int resIdx;
 399     int slotNum;
 400
 401     /** Resource Status */
 402     bool completed;
 403     bool squashed;
 404     bool processing;
 405     bool waiting;
 406 };
 407
 408 #endif //__CPU_INORDER_RESOURCE_HH__