2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
47 #include "cpu/inorder/resources/resource_list.hh"
48 #include "cpu/inorder/resource_pool.hh"
49 #include "debug/Resource.hh"
52 using namespace ThePipeline
;
54 ResourcePool::ResourcePool(InOrderCPU
*_cpu
, ThePipeline::Params
*params
)
55 : cpu(_cpu
), instUnit(NULL
), dataUnit(NULL
)
57 //@todo: use this function to instantiate the resources in resource pool.
58 //This will help in the auto-generation of this pipeline model.
59 //ThePipeline::addResources(resources, memObjects);
61 int stage_width
= cpu
->stageWidth
;
63 // Declare Resource Objects
64 // name - id - bandwidth - latency - CPU - Parameters
65 // --------------------------------------------------
66 resources
.push_back(new FetchSeqUnit("fetch_seq_unit", FetchSeq
,
67 stage_width
* 2, 0, _cpu
, params
));
69 // Keep track of the instruction fetch unit so we can easily
70 // provide a pointer to it in the CPU.
71 instUnit
= new FetchUnit("icache_port", ICache
,
72 stage_width
* 2 + MaxThreads
, 0, _cpu
,
74 resources
.push_back(instUnit
);
76 resources
.push_back(new DecodeUnit("decode_unit", Decode
,
77 stage_width
, 0, _cpu
, params
));
79 resources
.push_back(new BranchPredictor("branch_predictor", BPred
,
80 stage_width
, 0, _cpu
, params
));
82 resources
.push_back(new InstBuffer("fetch_buffer_t0", FetchBuff
, 4,
85 resources
.push_back(new UseDefUnit("regfile_manager", RegManager
,
86 stage_width
* 3, 0, _cpu
,
89 resources
.push_back(new AGENUnit("agen_unit", AGEN
,
90 stage_width
, 0, _cpu
, params
));
92 resources
.push_back(new ExecutionUnit("execution_unit", ExecUnit
,
93 stage_width
, 0, _cpu
, params
));
95 resources
.push_back(new MultDivUnit("mult_div_unit", MDU
,
101 // Keep track of the data load/store unit so we can easily provide
102 // a pointer to it in the CPU.
103 dataUnit
= new CacheUnit("dcache_port", DCache
,
104 stage_width
* 2 + MaxThreads
, 0, _cpu
,
106 resources
.push_back(dataUnit
);
108 gradObjects
.push_back(BPred
);
109 resources
.push_back(new GraduationUnit("graduation_unit", Grad
,
110 stage_width
, 0, _cpu
,
113 resources
.push_back(new InstBuffer("fetch_buffer_t1", FetchBuff2
, 4,
118 ResourcePool::~ResourcePool()
120 cout
<< "Deleting resources ..." << endl
;
122 for (int i
=0; i
< resources
.size(); i
++) {
123 DPRINTF(Resource
, "Deleting resource: %s.\n", resources
[i
]->name());
133 for (int i
=0; i
< resources
.size(); i
++) {
134 DPRINTF(Resource
, "Initializing resource: %s.\n",
135 resources
[i
]->name());
137 resources
[i
]->init();
144 return cpu
->name() + ".ResourcePool";
148 ResourcePool::print()
150 for (int i
=0; i
< resources
.size(); i
++) {
151 DPRINTF(InOrderDynInst
, "Res:%i %s\n",
152 i
, resources
[i
]->name());
159 ResourcePool::regStats()
161 DPRINTF(Resource
, "Registering Stats Throughout Resource Pool.\n");
163 int num_resources
= resources
.size();
165 for (int idx
= 0; idx
< num_resources
; idx
++) {
166 resources
[idx
]->regStats();
171 ResourcePool::getResIdx(const ThePipeline::ResourceId
&res_id
)
173 int num_resources
= resources
.size();
175 for (int idx
= 0; idx
< num_resources
; idx
++) {
176 if (resources
[idx
]->getId() == res_id
)
180 // todo: change return value to int and return a -1 here
181 // maybe even have enumerated type
183 panic("Can't find resource idx for: %i\n", res_id
);
189 ResourcePool::request(int res_idx
, DynInstPtr inst
)
191 //Make Sure This is a valid resource ID
192 assert(res_idx
>= 0 && res_idx
< resources
.size());
194 return resources
[res_idx
]->request(inst
);
198 ResourcePool::squash(DynInstPtr inst
, int res_idx
, InstSeqNum done_seq_num
,
201 resources
[res_idx
]->squash(inst
, ThePipeline::NumStages
-1, done_seq_num
,
206 ResourcePool::trap(Fault fault
, ThreadID tid
, DynInstPtr inst
)
208 DPRINTF(Resource
, "[tid:%i] Broadcasting Trap to all "
209 "resources.\n", tid
);
211 int num_resources
= resources
.size();
213 for (int idx
= 0; idx
< num_resources
; idx
++)
214 resources
[idx
]->trap(fault
, tid
, inst
);
218 ResourcePool::slotsAvail(int res_idx
)
220 return resources
[res_idx
]->slotsAvail();
224 ResourcePool::slotsInUse(int res_idx
)
226 return resources
[res_idx
]->slotsInUse();
229 //@todo: split this function and call this version schedulePoolEvent
230 // and use this scheduleEvent for scheduling a specific event on
232 //@todo: For arguments that arent being used in a ResPoolEvent, a dummyParam
233 // or some typedef can be used to signify what's important info
234 // to the event construction
236 ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type
, DynInstPtr inst
,
237 int delay
, int res_idx
, ThreadID tid
)
241 Tick when
= cpu
->nextCycle(curTick() + cpu
->ticks(delay
));
245 case ResourcePool::InstGraduated
:
247 DPRINTF(Resource
, "Scheduling Inst-Graduated Resource Pool "
248 "Event for tick %i.\n", curTick() + delay
);
249 ResPoolEventPri grad_pri
= ResGrad_Pri
;
250 ResPoolEvent
*res_pool_event
=
251 new ResPoolEvent(this,
254 inst
->squashingStage
,
258 cpu
->schedule(res_pool_event
, when
);
262 case ResourcePool::SquashAll
:
264 DPRINTF(Resource
, "Scheduling Squash Resource Pool Event for "
265 "tick %i.\n", curTick() + delay
);
266 ResPoolEventPri squash_pri
= ResSquash_Pri
;
267 ResPoolEvent
*res_pool_event
=
268 new ResPoolEvent(this,
271 inst
->squashingStage
,
275 cpu
->schedule(res_pool_event
, when
);
279 case ResourcePool::UpdateAfterContextSwitch
:
281 DPRINTF(Resource
, "Scheduling UpdatePC Resource Pool Event "
284 ResPoolEvent
*res_pool_event
= new ResPoolEvent(this,
287 inst
->squashingStage
,
290 cpu
->schedule(res_pool_event
, when
);
295 DPRINTF(Resource
, "Ignoring Unrecognized CPU Event (%s).\n",
296 InOrderCPU::eventNames
[e_type
]);
301 ResourcePool::unscheduleEvent(int res_idx
, DynInstPtr inst
)
303 resources
[res_idx
]->unscheduleEvent(inst
);
307 ResourcePool::squashAll(DynInstPtr inst
, int stage_num
,
308 InstSeqNum done_seq_num
, ThreadID tid
)
310 DPRINTF(Resource
, "[tid:%i] Broadcasting Squash All Event "
311 " starting w/stage %i for all instructions above [sn:%i].\n",
312 tid
, stage_num
, done_seq_num
);
314 int num_resources
= resources
.size();
316 for (int idx
= 0; idx
< num_resources
; idx
++) {
317 resources
[idx
]->squash(inst
, stage_num
, done_seq_num
, tid
);
322 ResourcePool::squashDueToMemStall(DynInstPtr inst
, int stage_num
,
323 InstSeqNum done_seq_num
, ThreadID tid
)
325 DPRINTF(Resource
, "[tid:%i] Broadcasting SquashDueToMemStall Event"
326 " starting w/stage %i for all instructions above [sn:%i].\n",
327 tid
, stage_num
, done_seq_num
);
329 int num_resources
= resources
.size();
331 for (int idx
= 0; idx
< num_resources
; idx
++) {
332 resources
[idx
]->squashDueToMemStall(inst
, stage_num
, done_seq_num
,
338 ResourcePool::activateThread(ThreadID tid
)
340 bool do_activate
= cpu
->threadModel
!= InOrderCPU::SwitchOnCacheMiss
||
341 cpu
->numActiveThreads() < 1 ||
342 cpu
->activeThreadId() == tid
;
346 DPRINTF(Resource
, "[tid:%i] Broadcasting Thread Activation to all "
347 "resources.\n", tid
);
349 int num_resources
= resources
.size();
351 for (int idx
= 0; idx
< num_resources
; idx
++) {
352 resources
[idx
]->activateThread(tid
);
355 DPRINTF(Resource
, "[tid:%i] Ignoring Thread Activation to all "
356 "resources.\n", tid
);
361 ResourcePool::deactivateThread(ThreadID tid
)
363 DPRINTF(Resource
, "[tid:%i] Broadcasting Thread Deactivation to all "
364 "resources.\n", tid
);
366 int num_resources
= resources
.size();
368 for (int idx
= 0; idx
< num_resources
; idx
++) {
369 resources
[idx
]->deactivateThread(tid
);
374 ResourcePool::suspendThread(ThreadID tid
)
376 DPRINTF(Resource
, "[tid:%i] Broadcasting Thread Suspension to all "
377 "resources.\n", tid
);
379 int num_resources
= resources
.size();
381 for (int idx
= 0; idx
< num_resources
; idx
++) {
382 resources
[idx
]->suspendThread(tid
);
387 ResourcePool::instGraduated(InstSeqNum seq_num
, ThreadID tid
)
389 DPRINTF(Resource
, "[tid:%i] Broadcasting [sn:%i] graduation to "
390 "appropriate resources.\n", tid
, seq_num
);
392 int num_resources
= gradObjects
.size();
394 for (int idx
= 0; idx
< num_resources
; idx
++) {
395 resources
[gradObjects
[idx
]]->instGraduated(seq_num
, tid
);
400 ResourcePool::updateAfterContextSwitch(DynInstPtr inst
, ThreadID tid
)
402 DPRINTF(Resource
, "[tid:%i] Broadcasting Update PC to all resources.\n",
405 int num_resources
= resources
.size();
407 for (int idx
= 0; idx
< num_resources
; idx
++) {
408 resources
[idx
]->updateAfterContextSwitch(inst
, tid
);
412 ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool
*_resPool
,
413 InOrderCPU::CPUEventType e_type
,
418 ResPoolEventPri res_pri
)
419 : Event(res_pri
), resPool(_resPool
),
420 eventType(e_type
), inst(_inst
), seqNum(seq_num
),
421 stageNum(stage_num
), tid(_tid
)
426 ResourcePool::ResPoolEvent::process()
428 switch ((int)eventType
)
431 case ResourcePool::InstGraduated
:
432 resPool
->instGraduated(seqNum
, tid
);
435 case ResourcePool::SquashAll
:
436 resPool
->squashAll(inst
, stageNum
, seqNum
, tid
);
439 case ResourcePool::UpdateAfterContextSwitch
:
440 resPool
->updateAfterContextSwitch(inst
, tid
);
444 fatal("Unrecognized Event Type");
447 resPool
->cpu
->cpuEventRemoveList
.push(this);
452 ResourcePool::ResPoolEvent::description() const
454 return "Resource Pool event";
457 /** Schedule resource event, regardless of its current state. */
459 ResourcePool::ResPoolEvent::scheduleEvent(int delay
)
461 InOrderCPU
*cpu
= resPool
->cpu
;
462 assert(!scheduled() || squashed());
463 cpu
->reschedule(this, cpu
->nextCycle(curTick() + cpu
->ticks(delay
)), true);
466 /** Unschedule resource event, regardless of its current state. */
468 ResourcePool::ResPoolEvent::unscheduleEvent()