2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
44 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
45 #define __CPU_INORDER_RESOURCE_POOL_HH__
50 #include "cpu/inorder/cpu.hh"
51 #include "cpu/inorder/inorder_dyn_inst.hh"
52 #include "cpu/inorder/params.hh"
53 #include "cpu/inorder/pipeline_traits.hh"
54 #include "cpu/inorder/resource.hh"
55 #include "cpu/inst_seq.hh"
56 #include "params/InOrderCPU.hh"
57 #include "sim/eventq.hh"
58 #include "sim/sim_object.hh"
67 typedef InOrderDynInst::DynInstPtr DynInstPtr;
70 // List of Resource Pool Events that extends
71 // the list started by the CPU
72 // NOTE(1): Resource Pool also uses event list
73 // CPUEventType defined in inorder/cpu.hh
74 enum ResPoolEventType {
75 InstGraduated = InOrderCPU::NumCPUEvents,
77 UpdateAfterContextSwitch,
81 enum ResPoolEventPri {
82 ResPool_Pri = InOrderCPU::InOrderCPU_Pri - 5,
87 class ResPoolEvent : public Event
91 ResourcePool *resPool;
94 InOrderCPU::CPUEventType eventType;
105 /** Constructs a resource event. */
106 ResPoolEvent(ResourcePool *_resPool,
107 InOrderCPU::CPUEventType e_type,
112 ResPoolEventPri res_pri = ResPool_Pri);
114 /** Set Type of Event To Be Scheduled */
115 void setEvent(InOrderCPU::CPUEventType e_type,
124 stageNum = stage_num;
128 /** Processes a resource event. */
131 /** Returns the description of the resource event. */
132 const char *description() const;
134 /** Schedule Event */
135 void scheduleEvent(Cycles delay);
137 /** Unschedule This Event */
138 void unscheduleEvent();
142 ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
143 virtual ~ResourcePool();
147 std::string name(int res_idx) { return resources[res_idx]->name(); }
153 /** Register Statistics in All Resources */
156 /** Returns a specific resource. */
157 unsigned getResIdx(const ThePipeline::ResourceId &res_id);
159 /** Returns a pointer to a resource */
160 Resource* getResource(int res_idx) { return resources[res_idx]; }
162 /** Request usage of this resource. Returns -1 if not granted and
163 * a positive request tag if granted.
165 ResReqPtr request(int res_idx, DynInstPtr inst);
167 /** Squash The Resource */
168 void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
171 /** Squash All Resources in Pool after Done Seq. Num */
172 void squashAll(DynInstPtr inst, int stage_num,
173 InstSeqNum done_seq_num, ThreadID tid);
175 /** Squash Resources in Pool after a memory stall
176 * NOTE: Only use during Switch-On-Miss Thread model
178 void squashDueToMemStall(DynInstPtr inst, int stage_num,
179 InstSeqNum done_seq_num, ThreadID tid);
181 /** Activate Thread in all resources */
182 void activateThread(ThreadID tid);
184 /** De-Activate Thread in all resources */
185 void deactivateThread(ThreadID tid);
187 /** Suspend Thread in all resources */
188 void suspendThread(ThreadID tid);
190 /** Broadcast Context Switch Update to all resources */
191 void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
193 /** Broadcast graduation to all resources */
194 void instGraduated(InstSeqNum seq_num, ThreadID tid);
196 /** Broadcast trap to all resources */
197 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
199 /** The number of instructions available that a resource can
202 int slotsAvail(int res_idx);
204 /** The number of instructions using a resource */
205 int slotsInUse(int res_idx);
207 /** Schedule resource event, regardless of its current state. */
208 void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
209 Cycles delay = Cycles(0), int res_idx = 0,
212 /** UnSchedule resource event, regardless of its current state. */
213 void unscheduleEvent(int res_idx, DynInstPtr inst);
215 /** Tasks to perform when simulation starts */
216 virtual void startup() { }
218 /** The CPU(s) that this resource interacts with */
221 DynInstPtr dummyInst[ThePipeline::MaxThreads];
224 * Get a pointer to the (always present) instruction fetch unit.
226 * @return the instruction unit
228 FetchUnit *getInstUnit() const { return instUnit; }
231 * Get a pointer to the (always present) data load/store unit.
233 * @return the data cache unit
235 CacheUnit *getDataUnit() const { return dataUnit; }
239 /** The instruction fetch unit. */
242 /** The data load/store unit. */
245 std::vector<Resource *> resources;
247 /** Resources that need to be updated on an inst. graduation */
248 std::vector<int> gradObjects;
251 #endif //__CPU_INORDER_RESOURCE_HH__