2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
44 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
45 #define __CPU_INORDER_RESOURCE_POOL_HH__
50 #include "cpu/inorder/cpu.hh"
51 #include "cpu/inorder/inorder_dyn_inst.hh"
52 #include "cpu/inorder/pipeline_traits.hh"
53 #include "cpu/inorder/resource.hh"
54 #include "cpu/inst_seq.hh"
55 #include "params/InOrderCPU.hh"
56 #include "sim/eventq.hh"
57 #include "sim/sim_object.hh"
66 typedef InOrderDynInst::DynInstPtr DynInstPtr;
69 // List of Resource Pool Events that extends
70 // the list started by the CPU
71 // NOTE(1): Resource Pool also uses event list
72 // CPUEventType defined in inorder/cpu.hh
73 enum ResPoolEventType {
74 InstGraduated = InOrderCPU::NumCPUEvents,
76 UpdateAfterContextSwitch,
80 enum ResPoolEventPri {
81 ResPool_Pri = InOrderCPU::InOrderCPU_Pri - 5,
86 class ResPoolEvent : public Event
90 ResourcePool *resPool;
93 InOrderCPU::CPUEventType eventType;
104 /** Constructs a resource event. */
105 ResPoolEvent(ResourcePool *_resPool,
106 InOrderCPU::CPUEventType e_type,
111 ResPoolEventPri res_pri = ResPool_Pri);
113 /** Set Type of Event To Be Scheduled */
114 void setEvent(InOrderCPU::CPUEventType e_type,
123 stageNum = stage_num;
127 /** Processes a resource event. */
130 /** Returns the description of the resource event. */
131 const char *description() const;
133 /** Schedule Event */
134 void scheduleEvent(Cycles delay);
136 /** Unschedule This Event */
137 void unscheduleEvent();
141 ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
142 virtual ~ResourcePool();
146 std::string name(int res_idx) { return resources[res_idx]->name(); }
152 /** Register Statistics in All Resources */
155 /** Returns a specific resource. */
156 unsigned getResIdx(const ThePipeline::ResourceId &res_id);
158 /** Returns a pointer to a resource */
159 Resource* getResource(int res_idx) { return resources[res_idx]; }
161 /** Request usage of this resource. Returns -1 if not granted and
162 * a positive request tag if granted.
164 ResReqPtr request(int res_idx, DynInstPtr inst);
166 /** Squash The Resource */
167 void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
170 /** Squash All Resources in Pool after Done Seq. Num */
171 void squashAll(DynInstPtr inst, int stage_num,
172 InstSeqNum done_seq_num, ThreadID tid);
174 /** Squash Resources in Pool after a memory stall
175 * NOTE: Only use during Switch-On-Miss Thread model
177 void squashDueToMemStall(DynInstPtr inst, int stage_num,
178 InstSeqNum done_seq_num, ThreadID tid);
180 /** Activate Thread in all resources */
181 void activateThread(ThreadID tid);
183 /** De-Activate Thread in all resources */
184 void deactivateThread(ThreadID tid);
186 /** Suspend Thread in all resources */
187 void suspendThread(ThreadID tid);
189 /** Broadcast Context Switch Update to all resources */
190 void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
192 /** Broadcast graduation to all resources */
193 void instGraduated(InstSeqNum seq_num, ThreadID tid);
195 /** Broadcast trap to all resources */
196 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
198 /** The number of instructions available that a resource can
201 int slotsAvail(int res_idx);
203 /** The number of instructions using a resource */
204 int slotsInUse(int res_idx);
206 /** Schedule resource event, regardless of its current state. */
207 void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
208 Cycles delay = Cycles(0), int res_idx = 0,
211 /** UnSchedule resource event, regardless of its current state. */
212 void unscheduleEvent(int res_idx, DynInstPtr inst);
214 /** Tasks to perform when simulation starts */
215 virtual void startup() { }
217 /** The CPU(s) that this resource interacts with */
220 DynInstPtr dummyInst[ThePipeline::MaxThreads];
223 * Get a pointer to the (always present) instruction fetch unit.
225 * @return the instruction unit
227 FetchUnit *getInstUnit() const { return instUnit; }
230 * Get a pointer to the (always present) data load/store unit.
232 * @return the data cache unit
234 CacheUnit *getDataUnit() const { return dataUnit; }
238 /** The instruction fetch unit. */
241 /** The data load/store unit. */
244 std::vector<Resource *> resources;
246 /** Resources that need to be updated on an inst. graduation */
247 std::vector<int> gradObjects;
250 #endif //__CPU_INORDER_RESOURCE_HH__