2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
33 #define __CPU_INORDER_RESOURCE_POOL_HH__
39 #include "cpu/inst_seq.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/resource.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/params.hh"
44 #include "params/InOrderCPU.hh"
45 #include "cpu/inorder/cpu.hh"
46 #include "sim/eventq.hh"
47 #include "sim/sim_object.hh"
56 typedef InOrderDynInst::DynInstPtr DynInstPtr;
59 // List of Resource Pool Events that extends
60 // the list started by the CPU
61 // NOTE(1): Resource Pool also uses event list
62 // CPUEventType defined in inorder/cpu.hh
63 enum ResPoolEventType {
64 InstGraduated = InOrderCPU::NumCPUEvents,
66 UpdateAfterContextSwitch,
70 class ResPoolEvent : public Event
74 ResourcePool *resPool;
77 InOrderCPU::CPUEventType eventType;
88 /** Constructs a resource event. */
89 ResPoolEvent(ResourcePool *_resPool);
91 /** Constructs a resource event. */
92 ResPoolEvent(ResourcePool *_resPool,
93 InOrderCPU::CPUEventType e_type,
99 /** Set Type of Event To Be Scheduled */
100 void setEvent(InOrderCPU::CPUEventType e_type,
109 stageNum = stage_num;
113 /** Processes a resource event. */
114 virtual void process();
116 /** Returns the description of the resource event. */
117 const char *description();
119 /** Schedule Event */
120 void scheduleEvent(int delay);
122 /** Unschedule This Event */
123 void unscheduleEvent();
127 ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
128 virtual ~ResourcePool() {}
132 std::string name(int res_idx) { return resources[res_idx]->name(); }
136 /** Register Statistics in All Resources */
139 /** Returns a specific port. */
140 Port* getPort(const std::string &if_name, int idx);
142 /** Returns a specific port. */
143 unsigned getPortIdx(const std::string &port_name);
145 /** Returns a specific resource. */
146 unsigned getResIdx(const std::string &res_name);
148 /** Returns a pointer to a resource */
149 Resource* getResource(int res_idx) { return resources[res_idx]; }
151 /** Request usage of this resource. Returns -1 if not granted and
152 * a positive request tag if granted.
154 ResReqPtr request(int res_idx, DynInstPtr inst);
156 /** Squash The Resource */
157 void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
160 /** Squash All Resources in Pool after Done Seq. Num */
161 void squashAll(DynInstPtr inst, int stage_num,
162 InstSeqNum done_seq_num, ThreadID tid);
164 /** Squash Resources in Pool after a memory stall
165 * NOTE: Only use during Switch-On-Miss Thread model
167 void squashDueToMemStall(DynInstPtr inst, int stage_num,
168 InstSeqNum done_seq_num, ThreadID tid);
170 /** Activate Thread in all resources */
171 void activateAll(ThreadID tid);
173 /** De-Activate Thread in all resources */
174 void deactivateAll(ThreadID tid);
176 /** De-Activate Thread in all resources */
177 void suspendAll(ThreadID tid);
179 /** Broadcast Context Switch Update to all resources */
180 void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
182 /** Broadcast graduation to all resources */
183 void instGraduated(InstSeqNum seq_num, ThreadID tid);
185 /** The number of instructions available that a resource can
188 int slotsAvail(int res_idx);
190 /** The number of instructions using a resource */
191 int slotsInUse(int res_idx);
193 /** Schedule resource event, regardless of its current state. */
194 void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
195 int delay = 0, int res_idx = 0, ThreadID tid = 0);
197 /** UnSchedule resource event, regardless of its current state. */
198 void unscheduleEvent(int res_idx, DynInstPtr inst);
200 /** Tasks to perform when simulation starts */
201 virtual void startup() { }
203 /** The CPU(s) that this resource interacts with */
206 DynInstPtr dummyInst[ThePipeline::MaxThreads];
209 std::vector<Resource *> resources;
211 std::vector<int> memObjects;
215 #endif //__CPU_INORDER_RESOURCE_HH__