src/cpu/inorder/resource_pool.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
  33 #define __CPU_INORDER_RESOURCE_POOL_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "cpu/inorder/cpu.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/params.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource.hh"
  44 #include "cpu/inst_seq.hh"
  45 #include "params/InOrderCPU.hh"
  46 #include "sim/eventq.hh"
  47 #include "sim/sim_object.hh"
  48
  49 class Event;
  50 class InOrderCPU;
  51 class Resource;
  52 class ResourceEvent;
  53
  54 class ResourcePool {
  55   public:
  56     typedef InOrderDynInst::DynInstPtr DynInstPtr;
  57
  58   public:
  59     // List of Resource Pool Events that extends
  60     // the list started by the CPU
  61     // NOTE(1): Resource Pool also uses event list
  62     // CPUEventType defined in inorder/cpu.hh
  63     enum ResPoolEventType {
  64         InstGraduated = InOrderCPU::NumCPUEvents,
  65         SquashAll,
  66         UpdateAfterContextSwitch,
  67         Default
  68     };
  69
  70     enum ResPoolEventPri {
  71         ResPool_Pri =  InOrderCPU::InOrderCPU_Pri - 5
  72     };
  73
  74     class ResPoolEvent : public Event
  75     {
  76       protected:
  77         /** Resource Pool */
  78         ResourcePool *resPool;
  79
  80       public:
  81         InOrderCPU::CPUEventType eventType;
  82
  83         DynInstPtr inst;
  84
  85         InstSeqNum seqNum;
  86
  87         int stageNum;
  88
  89         ThreadID tid;
  90
  91       public:
  92         /** Constructs a resource event. */
  93         ResPoolEvent(ResourcePool *_resPool,
  94                      InOrderCPU::CPUEventType e_type,
  95                      DynInstPtr _inst,
  96                      int stage_num,
  97                      InstSeqNum seq_num,
  98                      ThreadID _tid);
  99
 100         /** Set Type of Event To Be Scheduled */
 101         void setEvent(InOrderCPU::CPUEventType e_type,
 102                       DynInstPtr _inst,
 103                       int stage_num,
 104                       InstSeqNum seq_num,
 105                       ThreadID _tid)
 106         {
 107             eventType = e_type;
 108             inst = _inst;
 109             seqNum = seq_num;
 110             stageNum = stage_num;
 111             tid = _tid;
 112         }
 113
 114         /** Processes a resource event. */
 115         void process();
 116
 117         /** Returns the description of the resource event. */
 118         const char *description();
 119
 120         /** Schedule Event */
 121         void scheduleEvent(int delay);
 122
 123         /** Unschedule This Event */
 124         void unscheduleEvent();
 125     };
 126
 127   public:
 128     ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
 129     virtual ~ResourcePool();
 130
 131     std::string name();
 132
 133     std::string name(int res_idx) { return resources[res_idx]->name(); }
 134
 135     void init();
 136
 137     void print();
 138
 139     /** Register Statistics in All Resources */
 140     void regStats();
 141
 142     /** Returns a specific port. */
 143     Port* getPort(const std::string &if_name, int idx);
 144
 145     /** Returns a specific port. */
 146     unsigned getPortIdx(const std::string &port_name);
 147
 148     /** Returns a specific resource. */
 149     unsigned getResIdx(const std::string &res_name);
 150     unsigned getResIdx(const ThePipeline::ResourceId &res_id);
 151
 152     /** Returns a pointer to a resource */
 153     Resource* getResource(int res_idx) { return resources[res_idx]; }
 154
 155     /** Request usage of this resource. Returns -1 if not granted and
 156      *  a positive request tag if granted.
 157      */
 158     ResReqPtr request(int res_idx, DynInstPtr inst);
 159
 160     /** Squash The Resource */
 161     void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
 162                 ThreadID tid);
 163
 164     /** Squash All Resources in Pool after Done Seq. Num */
 165     void squashAll(DynInstPtr inst, int stage_num,
 166                    InstSeqNum done_seq_num, ThreadID tid);
 167
 168     /** Squash Resources in Pool after a memory stall
 169      *  NOTE: Only use during Switch-On-Miss Thread model
 170      */
 171     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 172                              InstSeqNum done_seq_num, ThreadID tid);
 173
 174     /** Activate Thread in all resources */
 175     void activateAll(ThreadID tid);
 176
 177     /** De-Activate Thread in all resources */
 178     void deactivateAll(ThreadID tid);
 179
 180     /** De-Activate Thread in all resources */
 181     void suspendAll(ThreadID tid);
 182
 183     /** Broadcast Context Switch Update to all resources */
 184     void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
 185
 186     /** Broadcast graduation to all resources */
 187     void instGraduated(InstSeqNum seq_num, ThreadID tid);
 188
 189     /** Broadcast trap to all resources */
 190     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 191
 192     /** The number of instructions available that a resource can
 193      *  can still process.
 194      */
 195     int slotsAvail(int res_idx);
 196
 197     /** The number of instructions using a resource */
 198     int slotsInUse(int res_idx);
 199
 200     /** Schedule resource event, regardless of its current state. */
 201     void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
 202                        int delay = 0, int res_idx = 0, ThreadID tid = 0);
 203
 204    /** UnSchedule resource event, regardless of its current state. */
 205     void unscheduleEvent(int res_idx, DynInstPtr inst);
 206
 207     /** Tasks to perform when simulation starts */
 208     virtual void startup() { }
 209
 210     /** The CPU(s) that this resource interacts with */
 211     InOrderCPU *cpu;
 212
 213     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 214
 215   private:
 216     std::vector<Resource *> resources;
 217
 218     std::vector<int> memObjects;
 219
 220 };
 221
 222 #endif //__CPU_INORDER_RESOURCE_HH__