2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
33 #define __CPU_INORDER_RESOURCE_POOL_HH__
39 #include "cpu/inorder/cpu.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/params.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/resource.hh"
44 #include "cpu/inst_seq.hh"
45 #include "params/InOrderCPU.hh"
46 #include "sim/eventq.hh"
47 #include "sim/sim_object.hh"
56 typedef InOrderDynInst::DynInstPtr DynInstPtr;
59 // List of Resource Pool Events that extends
60 // the list started by the CPU
61 // NOTE(1): Resource Pool also uses event list
62 // CPUEventType defined in inorder/cpu.hh
63 enum ResPoolEventType {
64 InstGraduated = InOrderCPU::NumCPUEvents,
66 UpdateAfterContextSwitch,
70 enum ResPoolEventPri {
71 ResPool_Pri = InOrderCPU::InOrderCPU_Pri - 5,
76 class ResPoolEvent : public Event
80 ResourcePool *resPool;
83 InOrderCPU::CPUEventType eventType;
94 /** Constructs a resource event. */
95 ResPoolEvent(ResourcePool *_resPool,
96 InOrderCPU::CPUEventType e_type,
101 ResPoolEventPri res_pri = ResPool_Pri);
103 /** Set Type of Event To Be Scheduled */
104 void setEvent(InOrderCPU::CPUEventType e_type,
113 stageNum = stage_num;
117 /** Processes a resource event. */
120 /** Returns the description of the resource event. */
121 const char *description();
123 /** Schedule Event */
124 void scheduleEvent(int delay);
126 /** Unschedule This Event */
127 void unscheduleEvent();
131 ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
132 virtual ~ResourcePool();
136 std::string name(int res_idx) { return resources[res_idx]->name(); }
142 /** Register Statistics in All Resources */
145 /** Returns a specific port. */
146 Port* getPort(const std::string &if_name, int idx);
148 /** Returns a specific port. */
149 unsigned getPortIdx(const std::string &port_name);
151 /** Returns a specific resource. */
152 unsigned getResIdx(const std::string &res_name);
153 unsigned getResIdx(const ThePipeline::ResourceId &res_id);
155 /** Returns a pointer to a resource */
156 Resource* getResource(int res_idx) { return resources[res_idx]; }
158 /** Request usage of this resource. Returns -1 if not granted and
159 * a positive request tag if granted.
161 ResReqPtr request(int res_idx, DynInstPtr inst);
163 /** Squash The Resource */
164 void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
167 /** Squash All Resources in Pool after Done Seq. Num */
168 void squashAll(DynInstPtr inst, int stage_num,
169 InstSeqNum done_seq_num, ThreadID tid);
171 /** Squash Resources in Pool after a memory stall
172 * NOTE: Only use during Switch-On-Miss Thread model
174 void squashDueToMemStall(DynInstPtr inst, int stage_num,
175 InstSeqNum done_seq_num, ThreadID tid);
177 /** Activate Thread in all resources */
178 void activateThread(ThreadID tid);
180 /** De-Activate Thread in all resources */
181 void deactivateThread(ThreadID tid);
183 /** Suspend Thread in all resources */
184 void suspendThread(ThreadID tid);
186 /** Broadcast Context Switch Update to all resources */
187 void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
189 /** Broadcast graduation to all resources */
190 void instGraduated(InstSeqNum seq_num, ThreadID tid);
192 /** Broadcast trap to all resources */
193 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
195 /** The number of instructions available that a resource can
198 int slotsAvail(int res_idx);
200 /** The number of instructions using a resource */
201 int slotsInUse(int res_idx);
203 /** Schedule resource event, regardless of its current state. */
204 void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
205 int delay = 0, int res_idx = 0, ThreadID tid = 0);
207 /** UnSchedule resource event, regardless of its current state. */
208 void unscheduleEvent(int res_idx, DynInstPtr inst);
210 /** Tasks to perform when simulation starts */
211 virtual void startup() { }
213 /** The CPU(s) that this resource interacts with */
216 DynInstPtr dummyInst[ThePipeline::MaxThreads];
219 std::vector<Resource *> resources;
221 /** Resources that interface with memory objects */
222 std::vector<int> memObjects;
224 /** Resources that need to be updated on an inst. graduation */
225 std::vector<int> gradObjects;
228 #endif //__CPU_INORDER_RESOURCE_HH__