src/cpu/inorder/resource_pool.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
  33 #define __CPU_INORDER_RESOURCE_POOL_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/resource.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/params.hh"
  44 #include "params/InOrderCPU.hh"
  45 #include "cpu/inorder/cpu.hh"
  46 #include "sim/eventq.hh"
  47 #include "sim/sim_object.hh"
  48
  49 class Event;
  50 class InOrderCPU;
  51 class Resource;
  52 class ResourceEvent;
  53
  54 class ResourcePool {
  55   public:
  56     typedef InOrderDynInst::DynInstPtr DynInstPtr;
  57
  58   public:
  59     // List of Resource Pool Events that extends
  60     // the list started by the CPU
  61     // NOTE(1): Resource Pool also uses event list
  62     // CPUEventType defined in inorder/cpu.hh
  63     enum ResPoolEventType {
  64         InstGraduated = InOrderCPU::NumCPUEvents,
  65         SquashAll,
  66         Default
  67     };
  68
  69     class ResPoolEvent : public Event
  70     {
  71       protected:
  72         /** Resource Pool */
  73         ResourcePool *resPool;
  74
  75       public:
  76         InOrderCPU::CPUEventType eventType;
  77
  78         DynInstPtr inst;
  79
  80         InstSeqNum seqNum;
  81
  82         int stageNum;
  83
  84         ThreadID tid;
  85
  86       public:
  87         /** Constructs a resource event. */
  88         ResPoolEvent(ResourcePool *_resPool);
  89
  90         /** Constructs a resource event. */
  91         ResPoolEvent(ResourcePool *_resPool,
  92                      InOrderCPU::CPUEventType e_type,
  93                      DynInstPtr _inst,
  94                      int stage_num,
  95                      InstSeqNum seq_num,
  96                      ThreadID _tid);
  97
  98         /** Set Type of Event To Be Scheduled */
  99         void setEvent(InOrderCPU::CPUEventType e_type,
 100                       DynInstPtr _inst,
 101                       int stage_num,
 102                       InstSeqNum seq_num,
 103                       ThreadID _tid)
 104         {
 105             eventType = e_type;
 106             inst = _inst;
 107             seqNum = seq_num;
 108             stageNum = stage_num;
 109             tid = _tid;
 110         }
 111
 112         /** Processes a resource event. */
 113         virtual void process();
 114
 115         /** Returns the description of the resource event. */
 116         const char *description();
 117
 118         /** Schedule Event */
 119         void scheduleEvent(int delay);
 120
 121         /** Unschedule This Event */
 122         void unscheduleEvent();
 123     };
 124
 125   public:
 126     ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
 127     virtual ~ResourcePool() {}
 128
 129     std::string name();
 130
 131     std::string name(int res_idx) { return resources[res_idx]->name(); }
 132
 133     void init();
 134
 135     /** Register Statistics in All Resources */
 136     void regStats();
 137
 138     /** Returns a specific port. */
 139     Port* getPort(const std::string &if_name, int idx);
 140
 141     /** Returns a specific port. */
 142     unsigned getPortIdx(const std::string &port_name);
 143
 144     /** Returns a specific resource. */
 145     unsigned getResIdx(const std::string &res_name);
 146
 147     /** Returns a pointer to a resource */
 148     Resource* getResource(int res_idx) { return resources[res_idx]; }
 149
 150     /** Request usage of this resource. Returns -1 if not granted and
 151      *  a positive request tag if granted.
 152      */
 153     ResReqPtr request(int res_idx, DynInstPtr inst);
 154
 155     /** Squash The Resource */
 156     void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
 157                 ThreadID tid);
 158
 159     /** Squash All Resources in Pool after Done Seq. Num */
 160     void squashAll(DynInstPtr inst, int stage_num,
 161                    InstSeqNum done_seq_num, ThreadID tid);
 162
 163     /** Squash Resources in Pool after a memory stall
 164      *  NOTE: Only use during Switch-On-Miss Thread model
 165      */
 166     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 167                              InstSeqNum done_seq_num, ThreadID tid);
 168
 169     /** Activate Thread in all resources */
 170     void activateAll(ThreadID tid);
 171
 172     /** De-Activate Thread in all resources */
 173     void deactivateAll(ThreadID tid);
 174
 175     /** De-Activate Thread in all resources */
 176     void suspendAll(ThreadID tid);
 177
 178     /** Broadcast graduation to all resources */
 179     void instGraduated(InstSeqNum seq_num, ThreadID tid);
 180
 181     /** The number of instructions available that a resource can
 182      *  can still process.
 183      */
 184     int slotsAvail(int res_idx);
 185
 186     /** The number of instructions using a resource */
 187     int slotsInUse(int res_idx);
 188
 189     /** Schedule resource event, regardless of its current state. */
 190     void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
 191                        int delay = 0, int res_idx = 0, ThreadID tid = 0);
 192
 193    /** UnSchedule resource event, regardless of its current state. */
 194     void unscheduleEvent(int res_idx, DynInstPtr inst);
 195
 196     /** Tasks to perform when simulation starts */
 197     virtual void startup() { }
 198
 199     /** The CPU(s) that this resource interacts with */
 200     InOrderCPU *cpu;
 201
 202     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 203
 204   private:
 205     std::vector<Resource *> resources;
 206
 207     std::vector<int> memObjects;
 208
 209 };
 210
 211 #endif //__CPU_INORDER_RESOURCE_HH__