src/cpu/inorder/resource_pool.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
  45 #define __CPU_INORDER_RESOURCE_POOL_HH__
  46
  47 #include <string>
  48 #include <vector>
  49
  50 #include "cpu/inorder/cpu.hh"
  51 #include "cpu/inorder/inorder_dyn_inst.hh"
  52 #include "cpu/inorder/params.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/resource.hh"
  55 #include "cpu/inst_seq.hh"
  56 #include "params/InOrderCPU.hh"
  57 #include "sim/eventq.hh"
  58 #include "sim/sim_object.hh"
  59
  60 class CacheUnit;
  61 class Event;
  62 class FetchUnit;
  63 class ResourceEvent;
  64
  65 class ResourcePool {
  66   public:
  67     typedef InOrderDynInst::DynInstPtr DynInstPtr;
  68
  69   public:
  70     // List of Resource Pool Events that extends
  71     // the list started by the CPU
  72     // NOTE(1): Resource Pool also uses event list
  73     // CPUEventType defined in inorder/cpu.hh
  74     enum ResPoolEventType {
  75         InstGraduated = InOrderCPU::NumCPUEvents,
  76         SquashAll,
  77         UpdateAfterContextSwitch,
  78         Default
  79     };
  80
  81     enum ResPoolEventPri {
  82         ResPool_Pri =  InOrderCPU::InOrderCPU_Pri - 5,
  83         ResGrad_Pri,
  84         ResSquash_Pri
  85     };
  86
  87     class ResPoolEvent : public Event
  88     {
  89       protected:
  90         /** Resource Pool */
  91         ResourcePool *resPool;
  92
  93       public:
  94         InOrderCPU::CPUEventType eventType;
  95
  96         DynInstPtr inst;
  97
  98         InstSeqNum seqNum;
  99
 100         int stageNum;
 101
 102         ThreadID tid;
 103
 104       public:
 105         /** Constructs a resource event. */
 106         ResPoolEvent(ResourcePool *_resPool,
 107                      InOrderCPU::CPUEventType e_type,
 108                      DynInstPtr _inst,
 109                      int stage_num,
 110                      InstSeqNum seq_num,
 111                      ThreadID _tid,
 112                      ResPoolEventPri res_pri = ResPool_Pri);
 113
 114         /** Set Type of Event To Be Scheduled */
 115         void setEvent(InOrderCPU::CPUEventType e_type,
 116                       DynInstPtr _inst,
 117                       int stage_num,
 118                       InstSeqNum seq_num,
 119                       ThreadID _tid)
 120         {
 121             eventType = e_type;
 122             inst = _inst;
 123             seqNum = seq_num;
 124             stageNum = stage_num;
 125             tid = _tid;
 126         }
 127
 128         /** Processes a resource event. */
 129         void process();
 130
 131         /** Returns the description of the resource event. */
 132         const char *description() const;
 133
 134         /** Schedule Event */
 135         void scheduleEvent(int delay);
 136
 137         /** Unschedule This Event */
 138         void unscheduleEvent();
 139     };
 140
 141   public:
 142     ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
 143     virtual ~ResourcePool();
 144
 145     std::string name();
 146
 147     std::string name(int res_idx) { return resources[res_idx]->name(); }
 148
 149     void init();
 150
 151     void print();
 152
 153     /** Register Statistics in All Resources */
 154     void regStats();
 155
 156     /** Returns a specific resource. */
 157     unsigned getResIdx(const ThePipeline::ResourceId &res_id);
 158
 159     /** Returns a pointer to a resource */
 160     Resource* getResource(int res_idx) { return resources[res_idx]; }
 161
 162     /** Request usage of this resource. Returns -1 if not granted and
 163      *  a positive request tag if granted.
 164      */
 165     ResReqPtr request(int res_idx, DynInstPtr inst);
 166
 167     /** Squash The Resource */
 168     void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
 169                 ThreadID tid);
 170
 171     /** Squash All Resources in Pool after Done Seq. Num */
 172     void squashAll(DynInstPtr inst, int stage_num,
 173                    InstSeqNum done_seq_num, ThreadID tid);
 174
 175     /** Squash Resources in Pool after a memory stall
 176      *  NOTE: Only use during Switch-On-Miss Thread model
 177      */
 178     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 179                              InstSeqNum done_seq_num, ThreadID tid);
 180
 181     /** Activate Thread in all resources */
 182     void activateThread(ThreadID tid);
 183
 184     /** De-Activate Thread in all resources */
 185     void deactivateThread(ThreadID tid);
 186
 187     /** Suspend Thread in all resources */
 188     void suspendThread(ThreadID tid);
 189
 190     /** Broadcast Context Switch Update to all resources */
 191     void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
 192
 193     /** Broadcast graduation to all resources */
 194     void instGraduated(InstSeqNum seq_num, ThreadID tid);
 195
 196     /** Broadcast trap to all resources */
 197     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 198
 199     /** The number of instructions available that a resource can
 200      *  can still process.
 201      */
 202     int slotsAvail(int res_idx);
 203
 204     /** The number of instructions using a resource */
 205     int slotsInUse(int res_idx);
 206
 207     /** Schedule resource event, regardless of its current state. */
 208     void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
 209                        int delay = 0, int res_idx = 0, ThreadID tid = 0);
 210
 211    /** UnSchedule resource event, regardless of its current state. */
 212     void unscheduleEvent(int res_idx, DynInstPtr inst);
 213
 214     /** Tasks to perform when simulation starts */
 215     virtual void startup() { }
 216
 217     /** The CPU(s) that this resource interacts with */
 218     InOrderCPU *cpu;
 219
 220     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 221
 222     /**
 223      * Get a pointer to the (always present) instruction fetch unit.
 224      *
 225      * @return the instruction unit
 226      */
 227     FetchUnit *getInstUnit() const { return instUnit; }
 228
 229     /**
 230      * Get a pointer to the (always present) data load/store unit.
 231      *
 232      * @return the data cache unit
 233      */
 234     CacheUnit *getDataUnit() const { return dataUnit; }
 235
 236   private:
 237
 238     /** The instruction fetch unit. */
 239     FetchUnit *instUnit;
 240
 241     /** The data load/store unit. */
 242     CacheUnit *dataUnit;
 243
 244     std::vector<Resource *> resources;
 245
 246     /** Resources that need to be updated on an inst. graduation */
 247     std::vector<int> gradObjects;
 248 };
 249
 250 #endif //__CPU_INORDER_RESOURCE_HH__