Merge ARM into the head. ARM will compile but may not actually work.
[gem5.git] / src / cpu / inorder / resource_pool.hh
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #ifndef __CPU_INORDER_RESOURCE_POOL_HH__
33 #define __CPU_INORDER_RESOURCE_POOL_HH__
34
35 #include <vector>
36 #include <list>
37 #include <string>
38
39 #include "cpu/inst_seq.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/resource.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/params.hh"
44 #include "params/InOrderCPU.hh"
45 #include "cpu/inorder/cpu.hh"
46 #include "sim/eventq.hh"
47 #include "sim/sim_object.hh"
48
49 class Event;
50 class InOrderCPU;
51 class Resource;
52 class ResourceEvent;
53
54 class ResourcePool {
55 public:
56 typedef InOrderDynInst::DynInstPtr DynInstPtr;
57
58 public:
59 // List of Resource Pool Events that extends
60 // the list started by the CPU
61 // NOTE(1): Resource Pool also uses event list
62 // CPUEventType defined in inorder/cpu.hh
63 enum ResPoolEventType {
64 InstGraduated = InOrderCPU::NumCPUEvents,
65 SquashAll,
66 Default
67 };
68
69 class ResPoolEvent : public Event
70 {
71 protected:
72 /** Resource Pool */
73 ResourcePool *resPool;
74
75 public:
76 InOrderCPU::CPUEventType eventType;
77
78 DynInstPtr inst;
79
80 InstSeqNum seqNum;
81
82 int stageNum;
83
84 unsigned tid;
85
86 public:
87 /** Constructs a resource event. */
88 ResPoolEvent(ResourcePool *_resPool);
89
90 /** Set Type of Event To Be Scheduled */
91 void setEvent(InOrderCPU::CPUEventType e_type,
92 DynInstPtr _inst,
93 int stage_num,
94 InstSeqNum seq_num,
95 unsigned _tid)
96 {
97 eventType = e_type;
98 inst = _inst;
99 seqNum = seq_num;
100 stageNum = stage_num;
101 tid = _tid;
102 }
103
104 /** Processes a resource event. */
105 virtual void process();
106
107 /** Returns the description of the resource event. */
108 const char *description();
109
110 /** Schedule Event */
111 void scheduleEvent(int delay);
112
113 /** Unschedule This Event */
114 void unscheduleEvent();
115 };
116
117 public:
118 ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
119 virtual ~ResourcePool() {}
120
121 std::string name();
122
123 std::string name(int res_idx) { return resources[res_idx]->name(); }
124
125 void init();
126
127 /** Register Statistics in All Resources */
128 void regStats();
129
130 /** Returns a specific port. */
131 Port* getPort(const std::string &if_name, int idx);
132
133 /** Returns a specific port. */
134 unsigned getPortIdx(const std::string &if_name);
135
136 Resource* getResource(int res_idx) { return resources[res_idx]; }
137
138 /** Request usage of this resource. Returns -1 if not granted and
139 * a positive request tag if granted.
140 */
141 ResReqPtr request(int res_idx, DynInstPtr inst);
142
143 /** Squash The Resource */
144 void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid);
145
146 /** Squash All Resources in Pool after Done Seq. Num */
147 void squashAll(DynInstPtr inst, int stage_num,
148 InstSeqNum done_seq_num, unsigned tid);
149
150 /** Activate Thread in all resources */
151 void activateAll(unsigned tid);
152
153 /** De-Activate Thread in all resources */
154 void deactivateAll(unsigned tid);
155
156 /** Broadcast graduation to all resources */
157 void instGraduated(InstSeqNum seq_num,unsigned tid);
158
159 /** The number of instructions available that a resource can
160 * can still process.
161 */
162 int slotsAvail(int res_idx);
163
164 /** The number of instructions using a resource */
165 int slotsInUse(int res_idx);
166
167 /** Schedule resource event, regardless of its current state. */
168 void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
169 int delay = 0, int res_idx = 0, int tid = 0);
170
171 /** UnSchedule resource event, regardless of its current state. */
172 void unscheduleEvent(int res_idx, DynInstPtr inst);
173
174 /** Tasks to perform when simulation starts */
175 virtual void startup() { }
176
177 /** The CPU(s) that this resource interacts with */
178 InOrderCPU *cpu;
179
180 DynInstPtr dummyInst[ThePipeline::MaxThreads];
181
182 private:
183 std::vector<Resource *> resources;
184
185 std::vector<int> memObjects;
186
187 };
188
189 #endif //__CPU_INORDER_RESOURCE_HH__