cpu: Update DRAM traffic gen
[gem5.git] / src / cpu / inorder / resources / agen_unit.cc
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #include "cpu/inorder/resources/agen_unit.hh"
33 #include "debug/InOrderAGEN.hh"
34
35 AGENUnit::AGENUnit(std::string res_name, int res_id, int res_width,
36 Cycles res_latency, InOrderCPU *_cpu,
37 ThePipeline::Params *params)
38 : Resource(res_name, res_id, res_width, res_latency, _cpu)
39 { }
40
41 void
42 AGENUnit::regStats()
43 {
44 agens
45 .name(name() + ".agens")
46 .desc("Number of Address Generations");
47
48 Resource::regStats();
49 }
50
51 void
52 AGENUnit::execute(int slot_num)
53 {
54 ResourceRequest* agen_req = reqs[slot_num];
55 DynInstPtr inst = reqs[slot_num]->inst;
56 #if TRACING_ON
57 ThreadID tid = inst->readTid();
58 #endif
59 InstSeqNum seq_num = inst->seqNum;
60
61 if (inst->fault != NoFault) {
62 DPRINTF(InOrderAGEN,
63 "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
64 "next stage.\n", tid, inst->seqNum, inst->fault->name(),
65 inst->pcState());
66 agen_req->done();
67 return;
68 }
69
70 switch (agen_req->cmd)
71 {
72 case GenerateAddr:
73 {
74 // Load/Store Instruction
75 if (inst->isMemRef()) {
76 DPRINTF(InOrderAGEN,
77 "[tid:%i] Generating Address for [sn:%i] (%s).\n",
78 tid, seq_num, inst->staticInst->getName());
79
80 inst->fault = inst->calcEA();
81 inst->setMemAddr(inst->getEA());
82
83 DPRINTF(InOrderAGEN,
84 "[tid:%i] [sn:%i] Effective address calculated as: %#x\n",
85 tid, seq_num, inst->getEA());
86
87 if (inst->fault == NoFault) {
88 agen_req->done();
89 } else {
90 fatal("%s encountered while calculating address [sn:%i] %s",
91 inst->fault->name(), seq_num, inst->instName());
92 }
93
94 agens++;
95 } else {
96 DPRINTF(InOrderAGEN,
97 "[tid:] Ignoring non-memory instruction [sn:%i]\n",
98 tid, seq_num);
99 agen_req->done();
100 }
101 }
102 break;
103
104 default:
105 fatal("Unrecognized command to %s", resName);
106 }
107 }