src/cpu/inorder/resources/branch_predictor.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/branch_predictor.hh"
  34 #include "debug/InOrderBPred.hh"
  35 #include "debug/InOrderStage.hh"
  36 #include "debug/Resource.hh"
  37
  38 using namespace std;
  39 using namespace TheISA;
  40 using namespace ThePipeline;
  41
  42 BranchPredictor::BranchPredictor(std::string res_name, int res_id,
  43                                  int res_width, Cycles res_latency,
  44                                  InOrderCPU *_cpu,
  45                                  ThePipeline::Params *params)
  46     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  47       branchPred(this, params)
  48 {
  49     instSize = sizeof(MachInst);
  50 }
  51
  52 void
  53 BranchPredictor::regStats()
  54 {
  55     predictedTaken
  56         .name(name() + ".predictedTaken")
  57         .desc("Number of Branches Predicted As Taken (True).");
  58
  59     predictedNotTaken
  60         .name(name() + ".predictedNotTaken")
  61         .desc("Number of Branches Predicted As Not Taken (False).");
  62
  63     Resource::regStats();
  64
  65     branchPred.regStats();
  66 }
  67
  68 void
  69 BranchPredictor::execute(int slot_num)
  70 {
  71     ResourceRequest* bpred_req = reqs[slot_num];
  72     DynInstPtr inst = bpred_req->inst;
  73     if (inst->fault != NoFault) {
  74         DPRINTF(InOrderBPred,
  75                 "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
  76                 "next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(),
  77                 inst->pcState());
  78         bpred_req->done();
  79         return;
  80     }
  81
  82     if (!inst->isControl()) {
  83         DPRINTF(Resource, "Ignoring %s, not a control inst.\n",
  84                 inst->instName());
  85         bpred_req->done();
  86         return;
  87     }
  88
  89     ThreadID tid = inst->readTid();
  90     InstSeqNum seq_num = inst->seqNum;
  91     switch (bpred_req->cmd)
  92     {
  93       case PredictBranch:
  94         {
  95             if (inst->seqNum > cpu->squashSeqNum[tid] &&
  96                 curTick() == cpu->lastSquashCycle[tid]) {
  97                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
  98                         "skipping prediction \n", tid, inst->seqNum);
  99             } else {
 100                 TheISA::PCState pred_PC = inst->pcState();
 101                 TheISA::advancePC(pred_PC, inst->staticInst);
 102
 103                 if (inst->isControl()) {
 104                     // If not, the pred_PC be updated to pc+8
 105                     // If predicted, the pred_PC will be updated to new target
 106                     // value
 107                     bool predict_taken = branchPred.predict(inst, pred_PC, tid);
 108
 109                     if (predict_taken) {
 110                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
 111                                 "predicted true.\n", tid, seq_num);
 112                         predictedTaken++;
 113                     } else {
 114                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
 115                                 "predicted false.\n", tid, seq_num);
 116                         predictedNotTaken++;
 117                     }
 118
 119                     inst->setBranchPred(predict_taken);
 120                 }
 121
 122                 //@todo: Check to see how hw_rei is handled here...how does PC,NPC get
 123                 //       updated to compare mispredict against???
 124                 inst->setPredTarg(pred_PC);
 125                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: %s Predicted PC is "
 126                         "%s.\n", tid, seq_num, inst->instName(), pred_PC);
 127             }
 128
 129             bpred_req->done();
 130         }
 131         break;
 132
 133       case UpdatePredictor:
 134         {
 135             if (inst->seqNum > cpu->squashSeqNum[tid] &&
 136                 curTick() == cpu->lastSquashCycle[tid]) {
 137                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
 138                         "skipping branch predictor update \n",
 139                         tid, inst->seqNum);
 140             } else {
 141                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating "
 142                         "Branch Predictor.\n",
 143                         tid, seq_num);
 144
 145
 146                 branchPred.update(seq_num, tid);
 147             }
 148
 149             bpred_req->done();
 150         }
 151         break;
 152
 153       default:
 154         fatal("Unrecognized command to %s", resName);
 155     }
 156 }
 157
 158 void
 159 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
 160                         InstSeqNum squash_seq_num, ThreadID tid)
 161 {
 162     InstSeqNum bpred_squash_num = inst->seqNum;
 163     DPRINTF(InOrderBPred, "[tid:%i][sn:%i] Squashing...\n", tid,
 164             bpred_squash_num);
 165
 166     // update due to branch resolution
 167     if (squash_stage >= ThePipeline::BackEndStartStage) {
 168         branchPred.squash(bpred_squash_num,
 169                           inst->pcState(),
 170                           inst->pcState().branching(),
 171                           tid);
 172     } else {
 173     // update due to predicted taken branch
 174         branchPred.squash(bpred_squash_num, tid);
 175     }
 176 }
 177
 178 void
 179 BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
 180 {
 181     branchPred.update(seq_num, tid);
 182 }