src/cpu/inorder/resources/branch_predictor.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/branch_predictor.hh"
  34
  35 using namespace std;
  36 using namespace TheISA;
  37 using namespace ThePipeline;
  38
  39 BranchPredictor::BranchPredictor(std::string res_name, int res_id, int res_width,
  40                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  41     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  42       branchPred(this, params)
  43 {
  44     instSize = sizeof(MachInst);
  45 }
  46
  47 void
  48 BranchPredictor::regStats()
  49 {
  50     predictedTaken
  51         .name(name() + ".predictedTaken")
  52         .desc("Number of Branches Predicted As Taken (True).");
  53
  54     predictedNotTaken
  55         .name(name() + ".predictedNotTaken")
  56         .desc("Number of Branches Predicted As Not Taken (False).");
  57
  58     Resource::regStats();
  59
  60     branchPred.regStats();
  61 }
  62
  63 void
  64 BranchPredictor::execute(int slot_num)
  65 {
  66     // After this is working, change this to a reinterpret cast
  67     // for performance considerations
  68     ResourceRequest* bpred_req = reqMap[slot_num];
  69
  70     DynInstPtr inst = bpred_req->inst;
  71     ThreadID tid = inst->readTid();
  72     int seq_num = inst->seqNum;
  73     //int stage_num = bpred_req->getStageNum();
  74
  75     bpred_req->fault = NoFault;
  76
  77     switch (bpred_req->cmd)
  78     {
  79       case PredictBranch:
  80         {
  81             Addr pred_PC = inst->readNextPC();
  82
  83             if (inst->isControl()) {
  84                 // If not, the pred_PC be updated to pc+8
  85                 // If predicted, the pred_PC will be updated to new target value
  86                 bool predict_taken = branchPred.predict(inst, pred_PC, tid);
  87
  88                 if (predict_taken) {
  89                     DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted true.\n",
  90                             tid, seq_num);
  91
  92                     inst->setPredTarg(pred_PC);
  93
  94                     predictedTaken++;
  95                 } else {
  96                     DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted false.\n",
  97                             tid, seq_num);
  98
  99                     if (inst->isCondDelaySlot())
 100                     {
 101                         inst->setPredTarg(inst->readPC() + (2 * instSize));
 102                     } else {
 103                         inst->setPredTarg(pred_PC);
 104                     }
 105
 106                     predictedNotTaken++;
 107                 }
 108
 109                 inst->setBranchPred(predict_taken);
 110
 111                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is %08p.\n",
 112                             tid, seq_num, pred_PC);
 113
 114             } else {
 115                 DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] because this isn't "
 116                         "a control instruction.\n", tid, seq_num);
 117             }
 118
 119             bpred_req->done();
 120         }
 121         break;
 122
 123       case UpdatePredictor:
 124         {
 125             DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating Branch Predictor.\n",
 126                     tid, seq_num);
 127
 128
 129             branchPred.update(seq_num, tid);
 130
 131             bpred_req->done();
 132         }
 133         break;
 134
 135       default:
 136         fatal("Unrecognized command to %s", resName);
 137     }
 138 }
 139
 140 void
 141 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
 142                         InstSeqNum squash_seq_num, ThreadID tid)
 143 {
 144     DPRINTF(InOrderBPred, "Squashing...\n");
 145     Addr corr_targ=inst->readPredPC();
 146     bool taken=inst->predTaken();
 147     branchPred.squash(squash_seq_num,corr_targ,taken,tid);
 148 }
 149
 150 void
 151 BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
 152 {
 153     branchPred.update(seq_num, tid);
 154 }