src/cpu/inorder/resources/branch_predictor.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/branch_predictor.hh"
  34
  35 using namespace std;
  36 using namespace TheISA;
  37 using namespace ThePipeline;
  38
  39 BranchPredictor::BranchPredictor(std::string res_name, int res_id, int res_width,
  40                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  41     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  42       branchPred(params)
  43 {
  44     instSize = sizeof(MachInst);
  45 }
  46
  47 void
  48 BranchPredictor::regStats()
  49 {
  50     predictedTaken
  51         .name(name() + ".predictedTaken")
  52         .desc("Number of Branches Predicted As Taken (True).");
  53
  54     predictedNotTaken
  55         .name(name() + ".predictedNotTaken")
  56         .desc("Number of Branches Predicted As Not Taken (False).");
  57
  58     Resource::regStats();
  59 }
  60
  61 void
  62 BranchPredictor::execute(int slot_num)
  63 {
  64     // After this is working, change this to a reinterpret cast
  65     // for performance considerations
  66     ResourceRequest* bpred_req = reqMap[slot_num];
  67
  68     DynInstPtr inst = bpred_req->inst;
  69     ThreadID tid = inst->readTid();
  70     int seq_num = inst->seqNum;
  71     //int stage_num = bpred_req->getStageNum();
  72
  73     bpred_req->fault = NoFault;
  74
  75     switch (bpred_req->cmd)
  76     {
  77       case PredictBranch:
  78         {
  79             Addr pred_PC = inst->readNextPC();
  80
  81             if (inst->isControl()) {
  82                 // If not, the pred_PC be updated to pc+8
  83                 // If predicted, the pred_PC will be updated to new target value
  84                 bool predict_taken = branchPred.predict(inst, pred_PC, tid);
  85
  86                 if (predict_taken) {
  87                     DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted true.\n",
  88                             tid, seq_num);
  89
  90                     inst->setPredTarg(pred_PC);
  91
  92                     predictedTaken++;
  93                 } else {
  94                     DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted false.\n",
  95                             tid, seq_num);
  96
  97                     if (inst->isCondDelaySlot())
  98                     {
  99                         inst->setPredTarg(inst->readPC() + (2 * instSize));
 100                     } else {
 101                         inst->setPredTarg(pred_PC);
 102                     }
 103
 104                     predictedNotTaken++;
 105                 }
 106
 107                 inst->setBranchPred(predict_taken);
 108
 109                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is %08p.\n",
 110                             tid, seq_num, pred_PC);
 111
 112             } else {
 113                 DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] because this isn't "
 114                         "a control instruction.\n", tid, seq_num);
 115             }
 116
 117             bpred_req->done();
 118         }
 119         break;
 120
 121       case UpdatePredictor:
 122         {
 123             DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating Branch Predictor.\n",
 124                     tid, seq_num);
 125
 126
 127             branchPred.update(seq_num, tid);
 128
 129             bpred_req->done();
 130         }
 131         break;
 132
 133       default:
 134         fatal("Unrecognized command to %s", resName);
 135     }
 136 }
 137
 138 void
 139 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
 140                         InstSeqNum squash_seq_num, ThreadID tid)
 141 {
 142     DPRINTF(InOrderBPred, "Squashing...\n");
 143     branchPred.squash(squash_seq_num, tid);
 144 }
 145
 146 void
 147 BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
 148 {
 149     branchPred.update(seq_num, tid);
 150 }