src/cpu/inorder/resources/branch_predictor.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/branch_predictor.hh"
  34
  35 using namespace std;
  36 using namespace TheISA;
  37 using namespace ThePipeline;
  38
  39 BranchPredictor::BranchPredictor(std::string res_name, int res_id, int res_width,
  40                                  int res_latency, InOrderCPU *_cpu,
  41                                  ThePipeline::Params *params)
  42     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  43       branchPred(this, params)
  44 {
  45     instSize = sizeof(MachInst);
  46 }
  47
  48 void
  49 BranchPredictor::regStats()
  50 {
  51     predictedTaken
  52         .name(name() + ".predictedTaken")
  53         .desc("Number of Branches Predicted As Taken (True).");
  54
  55     predictedNotTaken
  56         .name(name() + ".predictedNotTaken")
  57         .desc("Number of Branches Predicted As Not Taken (False).");
  58
  59     Resource::regStats();
  60
  61     branchPred.regStats();
  62 }
  63
  64 void
  65 BranchPredictor::execute(int slot_num)
  66 {
  67     // After this is working, change this to a reinterpret cast
  68     // for performance considerations
  69     ResourceRequest* bpred_req = reqs[slot_num];
  70     DynInstPtr inst = bpred_req->inst;
  71     ThreadID tid = inst->readTid();
  72     int seq_num = inst->seqNum;
  73
  74     switch (bpred_req->cmd)
  75     {
  76       case PredictBranch:
  77         {
  78             if (inst->seqNum > cpu->squashSeqNum[tid] &&
  79                 curTick() == cpu->lastSquashCycle[tid]) {
  80                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
  81                         "skipping prediction \n", tid, inst->seqNum);
  82             } else {
  83                 TheISA::PCState pred_PC = inst->pcState();
  84                 TheISA::advancePC(pred_PC, inst->staticInst);
  85 #if ISA_HAS_DELAY_SLOT
  86                 // By default set target to NNPC (e.g. PC + 8)
  87                 // so that a not-taken branch will update
  88                 // correctly
  89                 pred_PC.advance();
  90 #endif
  91
  92                 if (inst->isControl()) {
  93                     // If not, the pred_PC be updated to pc+8
  94                     // If predicted, the pred_PC will be updated to new target
  95                     // value
  96                     bool predict_taken = branchPred.predict(inst, pred_PC, tid);
  97
  98                     if (predict_taken) {
  99                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
 100                                 "predicted true.\n", tid, seq_num);
 101                         predictedTaken++;
 102                     } else {
 103                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
 104                                 "predicted false.\n", tid, seq_num);
 105                         predictedNotTaken++;
 106                     }
 107
 108                     inst->setBranchPred(predict_taken);
 109                 }
 110
 111                 inst->setPredTarg(pred_PC);
 112                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is "
 113                         "%s.\n", tid, seq_num, pred_PC);
 114             }
 115
 116             bpred_req->done();
 117         }
 118         break;
 119
 120       case UpdatePredictor:
 121         {
 122             if (inst->seqNum > cpu->squashSeqNum[tid] &&
 123                 curTick() == cpu->lastSquashCycle[tid]) {
 124                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
 125                         "skipping branch predictor update \n",
 126                         tid, inst->seqNum);
 127             } else {
 128                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating "
 129                         "Branch Predictor.\n",
 130                         tid, seq_num);
 131
 132
 133                 branchPred.update(seq_num, tid);
 134             }
 135
 136             bpred_req->done();
 137         }
 138         break;
 139
 140       default:
 141         fatal("Unrecognized command to %s", resName);
 142     }
 143 }
 144
 145 void
 146 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
 147                         InstSeqNum squash_seq_num, ThreadID tid)
 148 {
 149     DPRINTF(InOrderBPred, "[tid:%i][sn:%i] Squashing...\n", tid, inst->seqNum);
 150
 151 #if ISA_HAS_DELAY_SLOT
 152     // We need to squash the actual branch , NOT the delay slot
 153     // in the branch predictor
 154     squash_seq_num = squash_seq_num - 1;
 155 #endif
 156
 157     if (squash_stage >= ThePipeline::BackEndStartStage) {
 158         bool taken = inst->predTaken();
 159         branchPred.squash(squash_seq_num, inst->readPredTarg(), taken, tid);
 160     } else {
 161         branchPred.squash(squash_seq_num, tid);
 162     }
 163 }
 164
 165 void
 166 BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
 167 {
 168     branchPred.update(seq_num, tid);
 169 }