src/cpu/inorder/resources/branch_predictor.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "cpu/inorder/resources/branch_predictor.hh"
  33
  34 using namespace std;
  35 using namespace TheISA;
  36 using namespace ThePipeline;
  37
  38 BranchPredictor::BranchPredictor(std::string res_name, int res_id, int res_width,
  39                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  40     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  41       branchPred(params)
  42 {
  43     instSize = sizeof(MachInst);
  44 }
  45
  46 void
  47 BranchPredictor::regStats()
  48 {
  49     predictedTaken
  50         .name(name() + ".predictedTaken")
  51         .desc("Number of Branches Predicted As Taken (True).");
  52
  53     predictedNotTaken
  54         .name(name() + ".predictedNotTaken")
  55         .desc("Number of Branches Predicted As Not Taken (False).");
  56
  57     Resource::regStats();
  58 }
  59
  60 void
  61 BranchPredictor::execute(int slot_num)
  62 {
  63     // After this is working, change this to a reinterpret cast
  64     // for performance considerations
  65     ResourceRequest* bpred_req = reqMap[slot_num];
  66
  67     DynInstPtr inst = bpred_req->inst;
  68     int tid = inst->readTid();
  69     int seq_num = inst->seqNum;
  70     //int stage_num = bpred_req->getStageNum();
  71
  72     bpred_req->fault = NoFault;
  73
  74     switch (bpred_req->cmd)
  75     {
  76       case PredictBranch:
  77         {
  78             Addr pred_PC = inst->readNextPC();
  79
  80             if (inst->isControl()) {
  81                 // If predicted, the pred_PC will be updated to new target value
  82                 // If not, the pred_PC be updated to pc+8
  83                 bool predict_taken = branchPred.predict(inst, pred_PC, tid);
  84
  85                 if (predict_taken) {
  86                     DPRINTF(Resource, "[tid:%i]: [sn:%i]: Branch predicted true.\n",
  87                             tid, seq_num);
  88
  89                     inst->setPredTarg(pred_PC);
  90
  91                     predictedTaken++;
  92                 } else {
  93                     DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted false.\n",
  94                             tid, seq_num);
  95
  96                     if (inst->isCondDelaySlot())
  97                     {
  98                         inst->setPredTarg(inst->readPC() + (2 * instSize));
  99                     } else {
 100                         inst->setPredTarg(pred_PC);
 101                     }
 102
 103                     predictedNotTaken++;
 104                 }
 105
 106                 inst->setBranchPred(predict_taken);
 107
 108                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is %08p.\n",
 109                             tid, seq_num, pred_PC);
 110
 111             } else {
 112                 DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] because this isn't "
 113                         "a control instruction.\n", tid, seq_num);
 114             }
 115
 116             bpred_req->done();
 117         }
 118         break;
 119
 120       case UpdatePredictor:
 121         {
 122             DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating Branch Predictor.\n",
 123                     tid, seq_num);
 124
 125
 126             branchPred.update(seq_num, tid);
 127
 128             bpred_req->done();
 129         }
 130         break;
 131
 132       default:
 133         fatal("Unrecognized command to %s", resName);
 134     }
 135 }
 136
 137 void
 138 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
 139                         InstSeqNum squash_seq_num, unsigned tid)
 140 {
 141     DPRINTF(InOrderBPred, "Squashing...\n");
 142     branchPred.squash(squash_seq_num, tid);
 143 }
 144
 145 void
 146 BranchPredictor::instGraduated(InstSeqNum seq_num,unsigned tid)
 147 {
 148     branchPred.update(seq_num, tid);
 149 }