src/cpu/inorder/resources/branch_predictor.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/branch_predictor.hh"
  34 #include "debug/InOrderBPred.hh"
  35 #include "debug/InOrderStage.hh"
  36
  37 using namespace std;
  38 using namespace TheISA;
  39 using namespace ThePipeline;
  40
  41 BranchPredictor::BranchPredictor(std::string res_name, int res_id, int res_width,
  42                                  int res_latency, InOrderCPU *_cpu,
  43                                  ThePipeline::Params *params)
  44     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  45       branchPred(this, params)
  46 {
  47     instSize = sizeof(MachInst);
  48 }
  49
  50 void
  51 BranchPredictor::regStats()
  52 {
  53     predictedTaken
  54         .name(name() + ".predictedTaken")
  55         .desc("Number of Branches Predicted As Taken (True).");
  56
  57     predictedNotTaken
  58         .name(name() + ".predictedNotTaken")
  59         .desc("Number of Branches Predicted As Not Taken (False).");
  60
  61     Resource::regStats();
  62
  63     branchPred.regStats();
  64 }
  65
  66 void
  67 BranchPredictor::execute(int slot_num)
  68 {
  69     ResourceRequest* bpred_req = reqs[slot_num];
  70     DynInstPtr inst = bpred_req->inst;
  71     ThreadID tid = inst->readTid();
  72     InstSeqNum seq_num = inst->seqNum;
  73
  74     if (!inst->isControl()) {
  75         DPRINTF(Resource, "Ignoring %s, not a control inst.\n",
  76                 inst->instName());
  77         bpred_req->done();
  78         return;
  79     }
  80
  81
  82     switch (bpred_req->cmd)
  83     {
  84       case PredictBranch:
  85         {
  86             if (inst->seqNum > cpu->squashSeqNum[tid] &&
  87                 curTick() == cpu->lastSquashCycle[tid]) {
  88                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
  89                         "skipping prediction \n", tid, inst->seqNum);
  90             } else {
  91                 TheISA::PCState pred_PC = inst->pcState();
  92                 TheISA::advancePC(pred_PC, inst->staticInst);
  93
  94                 if (inst->isControl()) {
  95                     // If not, the pred_PC be updated to pc+8
  96                     // If predicted, the pred_PC will be updated to new target
  97                     // value
  98                     bool predict_taken = branchPred.predict(inst, pred_PC, tid);
  99
 100                     if (predict_taken) {
 101                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
 102                                 "predicted true.\n", tid, seq_num);
 103                         predictedTaken++;
 104                     } else {
 105                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
 106                                 "predicted false.\n", tid, seq_num);
 107                         predictedNotTaken++;
 108                     }
 109
 110                     inst->setBranchPred(predict_taken);
 111                 }
 112
 113                 inst->setPredTarg(pred_PC);
 114                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: %s Predicted PC is "
 115                         "%s.\n", tid, seq_num, inst->instName(), pred_PC);
 116             }
 117
 118             bpred_req->done();
 119         }
 120         break;
 121
 122       case UpdatePredictor:
 123         {
 124             if (inst->seqNum > cpu->squashSeqNum[tid] &&
 125                 curTick() == cpu->lastSquashCycle[tid]) {
 126                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
 127                         "skipping branch predictor update \n",
 128                         tid, inst->seqNum);
 129             } else {
 130                 DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating "
 131                         "Branch Predictor.\n",
 132                         tid, seq_num);
 133
 134
 135                 branchPred.update(seq_num, tid);
 136             }
 137
 138             bpred_req->done();
 139         }
 140         break;
 141
 142       default:
 143         fatal("Unrecognized command to %s", resName);
 144     }
 145 }
 146
 147 void
 148 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
 149                         InstSeqNum squash_seq_num, ThreadID tid)
 150 {
 151     DPRINTF(InOrderBPred, "[tid:%i][sn:%i] Squashing...\n", tid, inst->seqNum);
 152
 153 #if ISA_HAS_DELAY_SLOT
 154     // We need to squash the actual branch , NOT the delay slot
 155     // in the branch predictor
 156     squash_seq_num = squash_seq_num - 1;
 157 #endif
 158
 159     if (squash_stage >= ThePipeline::BackEndStartStage) {
 160         bool taken = inst->predTaken();
 161         branchPred.squash(squash_seq_num, inst->readPredTarg(), taken, tid);
 162     } else {
 163         branchPred.squash(squash_seq_num, tid);
 164     }
 165 }
 166
 167 void
 168 BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
 169 {
 170     branchPred.update(seq_num, tid);
 171 }