src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "base/hashmap.hh"
  42 #include "config/the_isa.hh"
  43 #include "cpu/inorder/inorder_dyn_inst.hh"
  44 #include "cpu/inorder/pipeline_traits.hh"
  45 #include "cpu/inorder/resource.hh"
  46 #include "mem/packet.hh"
  47 #include "mem/packet_access.hh"
  48 #include "mem/port.hh"
  49 #include "params/InOrderCPU.hh"
  50 #include "sim/sim_object.hh"
  51
  52 class CacheRequest;
  53 typedef CacheRequest* CacheReqPtr;
  54
  55 class CacheReqPacket;
  56 typedef CacheReqPacket* CacheReqPktPtr;
  57
  58 class CacheUnit : public Resource
  59 {
  60   public:
  61     typedef ThePipeline::DynInstPtr DynInstPtr;
  62
  63   public:
  64     CacheUnit(std::string res_name, int res_id, int res_width,
  65               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  66
  67     enum Command {
  68         InitiateReadData,
  69         CompleteReadData,
  70         InitiateWriteData,
  71         CompleteWriteData,
  72         InitSecondSplitRead,
  73         InitSecondSplitWrite,
  74         CompleteSecondSplitRead,
  75         CompleteSecondSplitWrite
  76     };
  77
  78   public:
  79     /** CachePort class for the Cache Unit.  Handles doing the
  80      * communication with the cache/memory.
  81      */
  82     class CachePort : public Port
  83     {
  84       protected:
  85         /** Pointer to cache port unit */
  86         CacheUnit *cachePortUnit;
  87
  88       public:
  89         /** Default constructor. */
  90         CachePort(CacheUnit *_cachePortUnit)
  91           : Port(_cachePortUnit->name() + "-cache-port",
  92                  (MemObject*)_cachePortUnit->cpu),
  93             cachePortUnit(_cachePortUnit)
  94         { }
  95
  96       protected:
  97         /** Atomic version of receive.  Panics. */
  98         Tick recvAtomic(PacketPtr pkt);
  99
 100         /** Functional version of receive.*/
 101         void recvFunctional(PacketPtr pkt);
 102
 103         /** Receives range changes. */
 104         void recvRangeChange();
 105
 106         /** Timing version of receive */
 107         bool recvTiming(PacketPtr pkt);
 108
 109         /** Handles doing a retry of a failed fetch. */
 110         void recvRetry();
 111     };
 112
 113     void init();
 114
 115     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 116                                 int res_idx, int slot_num,
 117                                 unsigned cmd);
 118
 119     ResReqPtr findRequest(DynInstPtr inst);
 120     ResReqPtr findRequest(DynInstPtr inst, int idx);
 121
 122     void requestAgain(DynInstPtr inst, bool &try_request);
 123
 124     virtual int getSlot(DynInstPtr inst);
 125
 126     /** Executes one of the commands from the "Command" enum */
 127     virtual void execute(int slot_num);
 128
 129     virtual void squash(DynInstPtr inst, int stage_num,
 130                 InstSeqNum squash_seq_num, ThreadID tid);
 131
 132     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 133                              InstSeqNum squash_seq_num, ThreadID tid);
 134
 135     virtual void squashCacheRequest(CacheReqPtr req_ptr);
 136
 137     /** After memory request is completedd in the cache, then do final
 138         processing to complete the request in the CPU.
 139     */
 140     virtual void processCacheCompletion(PacketPtr pkt);
 141
 142     /** Create request that will interface w/TLB and Memory objects */
 143     virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 144                                  int acc_size, int flags);
 145
 146     void finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req);
 147
 148     void buildDataPacket(CacheRequest *cache_req);
 149
 150     bool processSquash(CacheReqPacket *cache_pkt);
 151
 152     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 153
 154     void recvRetry();
 155
 156     /** Returns a specific port. */
 157     Port *getPort(const std::string &if_name, int idx);
 158
 159     Fault read(DynInstPtr inst, Addr addr,
 160                uint8_t *data, unsigned size, unsigned flags);
 161
 162     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 163                 Addr addr, unsigned flags, uint64_t *res);
 164
 165     void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 166                       int flags,  TheISA::TLB::Mode tlb_mode);
 167
 168     /** Read/Write on behalf of an instruction.
 169      *  curResSlot needs to be a valid value in instruction.
 170      */
 171     void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
 172                         CacheReqPtr split_req=NULL);
 173
 174     uint64_t getMemData(Packet *packet);
 175
 176     void setAddrDependency(DynInstPtr inst);
 177     virtual void removeAddrDependency(DynInstPtr inst);
 178
 179   protected:
 180     /** Cache interface. */
 181     CachePort *cachePort;
 182
 183     bool cachePortBlocked;
 184
 185     std::list<Addr> addrList[ThePipeline::MaxThreads];
 186
 187     m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 188
 189   public:
 190     int cacheBlkSize;
 191
 192     int cacheBlkMask;
 193
 194     /** Align a PC to the start of the Cache block. */
 195     Addr cacheBlockAlign(Addr addr)
 196     {
 197         return (addr & ~(cacheBlkMask));
 198     }
 199
 200     bool tlbBlocked[ThePipeline::MaxThreads];
 201     InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
 202
 203     TheISA::TLB* tlb();
 204     TheISA::TLB *_tlb;
 205 };
 206
 207 class CacheUnitEvent : public ResourceEvent {
 208   public:
 209     const std::string name() const
 210     {
 211         return "CacheUnitEvent";
 212     }
 213
 214
 215     /** Constructs a resource event. */
 216     CacheUnitEvent();
 217     virtual ~CacheUnitEvent() {}
 218
 219     /** Processes a resource event. */
 220     void process();
 221 };
 222
 223 //@todo: Move into CacheUnit Class for private access to "valid" field
 224 class CacheRequest : public ResourceRequest
 225 {
 226   public:
 227     CacheRequest(CacheUnit *cres)
 228         :  ResourceRequest(cres), memReq(NULL), reqData(NULL),
 229            dataPkt(NULL), memAccComplete(false),
 230            memAccPending(false), tlbStall(false), splitAccess(false),
 231            splitAccessNum(-1), split2ndAccess(false),
 232            fetchBufferFill(false)
 233     { }
 234
 235     virtual ~CacheRequest()
 236     {
 237         if (reqData && !splitAccess)
 238             delete [] reqData;
 239     }
 240
 241     void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
 242                     unsigned _cmd, MemCmd::Command pkt_cmd, int idx)
 243     {
 244         pktCmd = pkt_cmd;
 245         instIdx = idx;
 246
 247         ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
 248     }
 249
 250     void clearRequest();
 251
 252     virtual PacketDataPtr getData()
 253     { return reqData; }
 254
 255     void
 256     setMemAccCompleted(bool completed = true)
 257     {
 258         memAccComplete = completed;
 259     }
 260
 261     bool is2ndSplit()
 262     {
 263         return split2ndAccess;
 264     }
 265
 266     bool isMemAccComplete() { return memAccComplete; }
 267
 268     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 269     bool isMemAccPending() { return memAccPending; }
 270
 271     //Make this data private/protected!
 272     MemCmd::Command pktCmd;
 273     RequestPtr memReq;
 274     PacketDataPtr reqData;
 275     CacheReqPacket *dataPkt;
 276
 277     bool memAccComplete;
 278     bool memAccPending;
 279     bool tlbStall;
 280
 281     bool splitAccess;
 282     int splitAccessNum;
 283     bool split2ndAccess;
 284     int instIdx;
 285
 286     /** Should we expect block from cache access or fetch buffer? */
 287     bool fetchBufferFill;
 288 };
 289
 290 class CacheReqPacket : public Packet
 291 {
 292   public:
 293     CacheReqPacket(CacheRequest *_req,
 294                    Command _cmd, short _dest, int _idx = 0)
 295         : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
 296           instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
 297     {
 298
 299     }
 300
 301     CacheRequest *cacheReq;
 302     int instIdx;
 303     bool hasSlot;
 304     PacketDataPtr reqData;
 305     RequestPtr memReq;
 306 };
 307
 308 #endif //__CPU_CACHE_UNIT_HH__