src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "base/hashmap.hh"
  42 #include "config/the_isa.hh"
  43 #include "cpu/inorder/inorder_dyn_inst.hh"
  44 #include "cpu/inorder/pipeline_traits.hh"
  45 #include "cpu/inorder/resource.hh"
  46 #include "mem/packet.hh"
  47 #include "mem/packet_access.hh"
  48 #include "mem/port.hh"
  49 #include "params/InOrderCPU.hh"
  50 #include "sim/sim_object.hh"
  51
  52 class CacheReqPacket;
  53 typedef CacheReqPacket* CacheReqPktPtr;
  54
  55 class CacheUnit : public Resource
  56 {
  57   public:
  58     typedef ThePipeline::DynInstPtr DynInstPtr;
  59
  60   public:
  61     CacheUnit(std::string res_name, int res_id, int res_width,
  62               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  63
  64     enum Command {
  65         InitiateReadData,
  66         CompleteReadData,
  67         InitiateWriteData,
  68         CompleteWriteData,
  69         InitSecondSplitRead,
  70         InitSecondSplitWrite,
  71         CompleteSecondSplitRead,
  72         CompleteSecondSplitWrite
  73     };
  74
  75   public:
  76
  77     void init();
  78
  79     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
  80                                 int res_idx, int slot_num,
  81                                 unsigned cmd);
  82
  83     ResReqPtr findRequest(DynInstPtr inst);
  84     ResReqPtr findRequest(DynInstPtr inst, int idx);
  85
  86     void requestAgain(DynInstPtr inst, bool &try_request);
  87
  88     virtual int getSlot(DynInstPtr inst);
  89
  90     /** Executes one of the commands from the "Command" enum */
  91     virtual void execute(int slot_num);
  92
  93     virtual void squash(DynInstPtr inst, int stage_num,
  94                 InstSeqNum squash_seq_num, ThreadID tid);
  95
  96     void squashDueToMemStall(DynInstPtr inst, int stage_num,
  97                              InstSeqNum squash_seq_num, ThreadID tid);
  98
  99     virtual void squashCacheRequest(CacheReqPtr req_ptr);
 100
 101     /** After memory request is completedd in the cache, then do final
 102         processing to complete the request in the CPU.
 103     */
 104     virtual void processCacheCompletion(PacketPtr pkt);
 105
 106     /** Create request that will interface w/TLB and Memory objects */
 107     virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 108                                  int acc_size, int flags);
 109
 110     void finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req);
 111
 112     void buildDataPacket(CacheRequest *cache_req);
 113
 114     bool processSquash(CacheReqPacket *cache_pkt);
 115
 116     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 117
 118     void recvRetry();
 119
 120     Fault read(DynInstPtr inst, Addr addr,
 121                uint8_t *data, unsigned size, unsigned flags);
 122
 123     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 124                 Addr addr, unsigned flags, uint64_t *res);
 125
 126     void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 127                       int flags,  TheISA::TLB::Mode tlb_mode);
 128
 129     /** Read/Write on behalf of an instruction.
 130      *  curResSlot needs to be a valid value in instruction.
 131      */
 132     void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
 133                         CacheReqPtr split_req=NULL);
 134
 135     uint64_t getMemData(Packet *packet);
 136
 137     void setAddrDependency(DynInstPtr inst);
 138     virtual void removeAddrDependency(DynInstPtr inst);
 139
 140   protected:
 141     /** Cache interface. */
 142     MasterPort *cachePort;
 143
 144     bool cachePortBlocked;
 145
 146     std::list<Addr> addrList[ThePipeline::MaxThreads];
 147
 148     m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 149
 150   public:
 151     int cacheBlkSize;
 152
 153     int cacheBlkMask;
 154
 155     /** Align a PC to the start of the Cache block. */
 156     Addr cacheBlockAlign(Addr addr)
 157     {
 158         return (addr & ~(cacheBlkMask));
 159     }
 160
 161     bool tlbBlocked[ThePipeline::MaxThreads];
 162     InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
 163
 164     TheISA::TLB* tlb();
 165     TheISA::TLB *_tlb;
 166 };
 167
 168 class CacheUnitEvent : public ResourceEvent {
 169   public:
 170     const std::string name() const
 171     {
 172         return "CacheUnitEvent";
 173     }
 174
 175
 176     /** Constructs a resource event. */
 177     CacheUnitEvent();
 178     virtual ~CacheUnitEvent() {}
 179
 180     /** Processes a resource event. */
 181     void process();
 182 };
 183
 184 //@todo: Move into CacheUnit Class for private access to "valid" field
 185 class CacheRequest : public ResourceRequest
 186 {
 187   public:
 188     CacheRequest(CacheUnit *cres)
 189         :  ResourceRequest(cres), memReq(NULL), reqData(NULL),
 190            dataPkt(NULL), memAccComplete(false),
 191            memAccPending(false), tlbStall(false), splitAccess(false),
 192            splitAccessNum(-1), split2ndAccess(false),
 193            fetchBufferFill(false)
 194     { }
 195
 196     virtual ~CacheRequest()
 197     {
 198         if (reqData && !splitAccess)
 199             delete [] reqData;
 200     }
 201
 202     void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
 203                     unsigned _cmd, MemCmd::Command pkt_cmd, int idx)
 204     {
 205         pktCmd = pkt_cmd;
 206         instIdx = idx;
 207
 208         ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
 209     }
 210
 211     void clearRequest();
 212
 213     virtual PacketDataPtr getData()
 214     { return reqData; }
 215
 216     void
 217     setMemAccCompleted(bool completed = true)
 218     {
 219         memAccComplete = completed;
 220     }
 221
 222     bool is2ndSplit()
 223     {
 224         return split2ndAccess;
 225     }
 226
 227     bool isMemAccComplete() { return memAccComplete; }
 228
 229     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 230     bool isMemAccPending() { return memAccPending; }
 231
 232     //Make this data private/protected!
 233     MemCmd::Command pktCmd;
 234     RequestPtr memReq;
 235     PacketDataPtr reqData;
 236     CacheReqPacket *dataPkt;
 237
 238     bool memAccComplete;
 239     bool memAccPending;
 240     bool tlbStall;
 241
 242     bool splitAccess;
 243     int splitAccessNum;
 244     bool split2ndAccess;
 245     int instIdx;
 246
 247     /** Should we expect block from cache access or fetch buffer? */
 248     bool fetchBufferFill;
 249 };
 250
 251 class CacheReqPacket : public Packet
 252 {
 253   public:
 254     CacheReqPacket(CacheRequest *_req,
 255                    Command _cmd, short _dest, int _idx = 0)
 256         : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
 257           instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
 258     {
 259
 260     }
 261
 262     CacheRequest *cacheReq;
 263     int instIdx;
 264     bool hasSlot;
 265     PacketDataPtr reqData;
 266     RequestPtr memReq;
 267 };
 268
 269 #endif //__CPU_CACHE_UNIT_HH__