2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
33 #define __CPU_INORDER_CACHE_UNIT_HH__
39 #include "arch/predecoder.hh"
40 #include "arch/tlb.hh"
41 #include "base/hashmap.hh"
42 #include "config/the_isa.hh"
43 #include "cpu/inorder/inorder_dyn_inst.hh"
44 #include "cpu/inorder/pipeline_traits.hh"
45 #include "cpu/inorder/resource.hh"
46 #include "mem/packet.hh"
47 #include "mem/packet_access.hh"
48 #include "mem/port.hh"
49 #include "params/InOrderCPU.hh"
50 #include "sim/sim_object.hh"
53 typedef CacheRequest* CacheReqPtr;
56 typedef CacheReqPacket* CacheReqPktPtr;
58 class CacheUnit : public Resource
61 typedef ThePipeline::DynInstPtr DynInstPtr;
64 CacheUnit(std::string res_name, int res_id, int res_width,
65 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
74 CompleteSecondSplitRead,
75 CompleteSecondSplitWrite
79 /** CachePort class for the Cache Unit. Handles doing the
80 * communication with the cache/memory.
82 class CachePort : public Port
85 /** Pointer to cache port unit */
86 CacheUnit *cachePortUnit;
89 /** Default constructor. */
90 CachePort(CacheUnit *_cachePortUnit)
91 : Port(_cachePortUnit->name() + "-cache-port",
92 (MemObject*)_cachePortUnit->cpu),
93 cachePortUnit(_cachePortUnit)
97 /** Atomic version of receive. Panics. */
98 Tick recvAtomic(PacketPtr pkt);
100 /** Functional version of receive.*/
101 void recvFunctional(PacketPtr pkt);
103 /** Receives range changes. */
104 void recvRangeChange();
106 /** Timing version of receive */
107 bool recvTiming(PacketPtr pkt);
109 /** Handles doing a retry of a failed fetch. */
115 ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
116 int res_idx, int slot_num,
119 ResReqPtr findRequest(DynInstPtr inst);
120 ResReqPtr findRequest(DynInstPtr inst, int idx);
122 void requestAgain(DynInstPtr inst, bool &try_request);
124 virtual int getSlot(DynInstPtr inst);
126 /** Executes one of the commands from the "Command" enum */
127 virtual void execute(int slot_num);
129 virtual void squash(DynInstPtr inst, int stage_num,
130 InstSeqNum squash_seq_num, ThreadID tid);
132 void squashDueToMemStall(DynInstPtr inst, int stage_num,
133 InstSeqNum squash_seq_num, ThreadID tid);
135 virtual void squashCacheRequest(CacheReqPtr req_ptr);
137 /** After memory request is completedd in the cache, then do final
138 processing to complete the request in the CPU.
140 virtual void processCacheCompletion(PacketPtr pkt);
142 /** Create request that will interface w/TLB and Memory objects */
143 virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
144 int acc_size, int flags);
146 void finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req);
148 void buildDataPacket(CacheRequest *cache_req);
150 bool processSquash(CacheReqPacket *cache_pkt);
153 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
157 /** Returns a specific port. */
158 Port *getPort(const std::string &if_name, int idx);
160 Fault read(DynInstPtr inst, Addr addr,
161 uint8_t *data, unsigned size, unsigned flags);
163 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
164 Addr addr, unsigned flags, uint64_t *res);
166 void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
167 int flags, TheISA::TLB::Mode tlb_mode);
169 /** Read/Write on behalf of an instruction.
170 * curResSlot needs to be a valid value in instruction.
172 void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
173 CacheReqPtr split_req=NULL);
175 uint64_t getMemData(Packet *packet);
177 void setAddrDependency(DynInstPtr inst);
178 virtual void removeAddrDependency(DynInstPtr inst);
181 /** Cache interface. */
182 CachePort *cachePort;
184 bool cachePortBlocked;
186 std::list<Addr> addrList[ThePipeline::MaxThreads];
188 m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
195 /** Align a PC to the start of the Cache block. */
196 Addr cacheBlockAlign(Addr addr)
198 return (addr & ~(cacheBlkMask));
201 bool tlbBlocked[ThePipeline::MaxThreads];
202 InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
208 class CacheUnitEvent : public ResourceEvent {
210 const std::string name() const
212 return "CacheUnitEvent";
216 /** Constructs a resource event. */
218 virtual ~CacheUnitEvent() {}
220 /** Processes a resource event. */
224 //@todo: Move into CacheUnit Class for private access to "valid" field
225 class CacheRequest : public ResourceRequest
228 CacheRequest(CacheUnit *cres)
229 : ResourceRequest(cres), memReq(NULL), reqData(NULL),
230 dataPkt(NULL), memAccComplete(false),
231 memAccPending(false), tlbStall(false), splitAccess(false),
232 splitAccessNum(-1), split2ndAccess(false),
233 fetchBufferFill(false)
236 virtual ~CacheRequest()
238 if (reqData && !splitAccess)
242 void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
243 unsigned _cmd, MemCmd::Command pkt_cmd, int idx)
248 ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
253 virtual PacketDataPtr getData()
257 setMemAccCompleted(bool completed = true)
259 memAccComplete = completed;
264 return split2ndAccess;
267 bool isMemAccComplete() { return memAccComplete; }
269 void setMemAccPending(bool pending = true) { memAccPending = pending; }
270 bool isMemAccPending() { return memAccPending; }
272 //Make this data private/protected!
273 MemCmd::Command pktCmd;
275 PacketDataPtr reqData;
276 CacheReqPacket *dataPkt;
287 /** Should we expect block from cache access or fetch buffer? */
288 bool fetchBufferFill;
291 class CacheReqPacket : public Packet
294 CacheReqPacket(CacheRequest *_req,
295 Command _cmd, short _dest, int _idx = 0)
296 : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
297 instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
302 CacheRequest *cacheReq;
305 PacketDataPtr reqData;
309 #endif //__CPU_CACHE_UNIT_HH__