src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 //#include "cpu/inorder/params.hh"
  40
  41 #include "cpu/inorder/resource.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "mem/packet.hh"
  44 #include "mem/packet_access.hh"
  45 #include "mem/port.hh"
  46 #include "cpu/inorder/pipeline_traits.hh"
  47 #include "sim/sim_object.hh"
  48
  49 #include "params/InOrderCPU.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65     virtual ~CacheUnit() {}
  66
  67     enum Command {
  68         InitiateFetch,
  69         CompleteFetch,
  70         InitiateReadData,
  71         CompleteReadData,
  72         InitiateWriteData,
  73         CompleteWriteData,
  74         Fetch,
  75         ReadData,
  76         WriteData
  77     };
  78
  79   public:
  80     /** CachePort class for the Cache Unit.  Handles doing the
  81      * communication with the cache/memory.
  82      */
  83     class CachePort : public Port
  84     {
  85       protected:
  86         /** Pointer to cache port unit */
  87         CacheUnit *cachePortUnit;
  88
  89       public:
  90         /** Default constructor. */
  91         CachePort(CacheUnit *_cachePortUnit)
  92           : Port(_cachePortUnit->name() + "-cache-port",
  93                  (MemObject*)_cachePortUnit->cpu),
  94             cachePortUnit(_cachePortUnit)
  95         { }
  96
  97         bool snoopRangeSent;
  98
  99       protected:
 100         /** Atomic version of receive.  Panics. */
 101         virtual Tick recvAtomic(PacketPtr pkt);
 102
 103         /** Functional version of receive.  Panics. */
 104         virtual void recvFunctional(PacketPtr pkt);
 105
 106         /** Receives status change.  Other than range changing, panics. */
 107         virtual void recvStatusChange(Status status);
 108
 109         /** Returns the address ranges of this device. */
 110         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 111                                             AddrRangeList &snoop)
 112         { resp.clear(); snoop.clear(); }
 113
 114         /** Timing version of receive. Handles setting fetch to the
 115          * proper status to start fetching. */
 116         virtual bool recvTiming(PacketPtr pkt);
 117
 118         /** Handles doing a retry of a failed fetch. */
 119         virtual void recvRetry();
 120     };
 121
 122     enum CachePortStatus {
 123         cacheWaitResponse,
 124         cacheWaitRetry,
 125         cacheAccessComplete
 126     };
 127
 128     ///virtual void init();
 129
 130     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 131                                         int res_idx, int slot_num,
 132                                         unsigned cmd);
 133
 134     void requestAgain(DynInstPtr inst, bool &try_request);
 135
 136     int getSlot(DynInstPtr inst);
 137
 138     void freeSlot(int slot_num);
 139
 140     /** Execute the function of this resource. The Default is action
 141      *  is to do nothing. More specific models will derive from this
 142      *  class and define their own execute function.
 143      */
 144     void execute(int slot_num);
 145
 146     void squash(DynInstPtr inst, int stage_num,
 147                 InstSeqNum squash_seq_num, unsigned tid);
 148
 149     /** Processes cache completion event. */
 150     void processCacheCompletion(PacketPtr pkt);
 151
 152     void recvRetry();
 153
 154     /** Align a PC to the start of an I-cache block. */
 155     Addr cacheBlockAlignPC(Addr addr)
 156     {
 157         //addr = TheISA::realPCToFetchPC(addr);
 158         return (addr & ~(cacheBlkMask));
 159     }
 160
 161     /** Returns a specific port. */
 162     Port *getPort(const std::string &if_name, int idx);
 163
 164     /** Fetch on behalf of an instruction. Will check to see
 165      *  if instruction is actually in resource before
 166      *  trying to fetch.
 167      */
 168     //Fault doFetchAccess(DynInstPtr inst);
 169
 170     /** Read/Write on behalf of an instruction.
 171      *  curResSlot needs to be a valid value in instruction.
 172      */
 173     Fault doDataAccess(DynInstPtr inst);
 174
 175     void prefetch(DynInstPtr inst);
 176
 177     void writeHint(DynInstPtr inst);
 178
 179     uint64_t getMemData(Packet *packet);
 180
 181   protected:
 182     /** Cache interface. */
 183     CachePort *cachePort;
 184
 185     CachePortStatus cacheStatus;
 186
 187     CacheReqPtr retryReq;
 188
 189     PacketPtr retryPkt;
 190
 191     int retrySlot;
 192
 193     bool cacheBlocked;
 194
 195     std::vector<Addr> addrList;
 196
 197     std::map<Addr, InstSeqNum> addrMap;
 198
 199   public:
 200     int cacheBlkSize;
 201
 202     int cacheBlkMask;
 203
 204     /** Align a PC to the start of the Cache block. */
 205     Addr cacheBlockAlign(Addr addr)
 206     {
 207         return (addr & ~(cacheBlkMask));
 208     }
 209
 210     /** THINGS USED FOR FETCH */
 211     // NO LONGER USED BY COMMENT OUT UNTIL FULL VERIFICATION
 212     /** The mem line being fetched. */
 213     //uint8_t *cacheData[ThePipeline::MaxThreads];
 214
 215     /** The Addr of the cacheline that has been loaded. */
 216     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 217
 218     //unsigned fetchOffset[ThePipeline::MaxThreads];
 219
 220     /** @todo: Add Resource Stats Here */
 221 };
 222
 223 struct CacheSchedEntry : public ThePipeline::ScheduleEntry
 224 {
 225     enum EntryType {
 226         FetchAccess,
 227         DataAccess
 228     };
 229
 230     CacheSchedEntry(int stage_num, int _priority, int res_num,
 231                     MemCmd::Command pkt_cmd, EntryType _type = FetchAccess)
 232         : ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
 233           type(_type)
 234     { }
 235
 236     MemCmd::Command pktCmd;
 237     EntryType type;
 238 };
 239
 240 class CacheRequest : public ResourceRequest
 241 {
 242   public:
 243     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 244                  int slot_num, unsigned cmd, int req_size,
 245                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
 246         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 247           pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
 248     {
 249         memReq = inst->memReq;
 250
 251         reqData = new uint8_t[req_size];
 252         retryPkt = NULL;
 253     }
 254
 255     virtual ~CacheRequest()
 256     {
 257 #if 0
 258         delete reqData;
 259
 260         // Can get rid of packet and packet request now
 261         if (*dataPkt) {
 262             if (*dataPkt->req) {
 263                 delete dataPkt->req;
 264             }
 265             delete dataPkt;
 266         }
 267
 268         // Can get rid of packet and packet request now
 269         if (retryPkt) {
 270             if (retryPkt->req) {
 271                 delete retryPkt->req;
 272             }
 273             delete retryPkt;
 274         }
 275 #endif
 276
 277         if (memReq)
 278             delete memReq;
 279     }
 280
 281     virtual PacketDataPtr getData()
 282     {   return reqData; }
 283
 284     void
 285     setMemAccCompleted(bool completed = true)
 286     {
 287         memAccComplete = completed;
 288     }
 289
 290     bool isMemAccComplete() { return memAccComplete; }
 291
 292     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 293     bool isMemAccPending() { return memAccPending; }
 294
 295     //Make this data private/protected!
 296     MemCmd::Command pktCmd;
 297     RequestPtr memReq;
 298     PacketDataPtr reqData;
 299     PacketPtr dataPkt;
 300     PacketPtr retryPkt;
 301
 302     bool memAccComplete;
 303     bool memAccPending;
 304 };
 305
 306 class CacheReqPacket : public Packet
 307 {
 308   public:
 309     CacheReqPacket(CacheRequest *_req,
 310                    Command _cmd, short _dest)
 311         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
 312     {
 313
 314     }
 315
 316     CacheRequest *cacheReq;
 317 };
 318
 319 #endif //__CPU_CACHE_UNIT_HH__