src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "cpu/inorder/resource.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "mem/packet.hh"
  43 #include "mem/packet_access.hh"
  44 #include "mem/port.hh"
  45 #include "cpu/inorder/pipeline_traits.hh"
  46 #include "sim/sim_object.hh"
  47
  48 #include "params/InOrderCPU.hh"
  49
  50 class CacheRequest;
  51 typedef CacheRequest* CacheReqPtr;
  52
  53 class CacheReqPacket;
  54 typedef CacheReqPacket* CacheReqPktPtr;
  55
  56 class CacheUnit : public Resource
  57 {
  58   public:
  59     typedef ThePipeline::DynInstPtr DynInstPtr;
  60
  61   public:
  62     CacheUnit(std::string res_name, int res_id, int res_width,
  63               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  64     virtual ~CacheUnit() {}
  65
  66     enum Command {
  67         InitiateFetch,
  68         CompleteFetch,
  69         InitiateReadData,
  70         CompleteReadData,
  71         InitiateWriteData,
  72         CompleteWriteData,
  73         Fetch,
  74         ReadData,
  75         WriteData
  76     };
  77
  78   public:
  79     /** CachePort class for the Cache Unit.  Handles doing the
  80      * communication with the cache/memory.
  81      */
  82     class CachePort : public Port
  83     {
  84       protected:
  85         /** Pointer to cache port unit */
  86         CacheUnit *cachePortUnit;
  87
  88       public:
  89         /** Default constructor. */
  90         CachePort(CacheUnit *_cachePortUnit)
  91           : Port(_cachePortUnit->name() + "-cache-port",
  92                  (MemObject*)_cachePortUnit->cpu),
  93             cachePortUnit(_cachePortUnit)
  94         { }
  95
  96         bool snoopRangeSent;
  97
  98       protected:
  99         /** Atomic version of receive.  Panics. */
 100         virtual Tick recvAtomic(PacketPtr pkt);
 101
 102         /** Functional version of receive.  Panics. */
 103         virtual void recvFunctional(PacketPtr pkt);
 104
 105         /** Receives status change.  Other than range changing, panics. */
 106         virtual void recvStatusChange(Status status);
 107
 108         /** Returns the address ranges of this device. */
 109         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 110                                             AddrRangeList &snoop)
 111         { resp.clear(); snoop.clear(); }
 112
 113         /** Timing version of receive. Handles setting fetch to the
 114          * proper status to start fetching. */
 115         virtual bool recvTiming(PacketPtr pkt);
 116
 117         /** Handles doing a retry of a failed fetch. */
 118         virtual void recvRetry();
 119     };
 120
 121     enum CachePortStatus {
 122         cacheWaitResponse,
 123         cacheWaitRetry,
 124         cacheAccessComplete
 125     };
 126
 127     ///virtual void init();
 128
 129     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 130                                         int res_idx, int slot_num,
 131                                         unsigned cmd);
 132
 133     void requestAgain(DynInstPtr inst, bool &try_request);
 134
 135     int getSlot(DynInstPtr inst);
 136
 137     void freeSlot(int slot_num);
 138
 139     /** Execute the function of this resource. The Default is action
 140      *  is to do nothing. More specific models will derive from this
 141      *  class and define their own execute function.
 142      */
 143     void execute(int slot_num);
 144
 145     void squash(DynInstPtr inst, int stage_num,
 146                 InstSeqNum squash_seq_num, unsigned tid);
 147
 148     /** Processes cache completion event. */
 149     void processCacheCompletion(PacketPtr pkt);
 150
 151     void recvRetry();
 152
 153     /** Align a PC to the start of an I-cache block. */
 154     Addr cacheBlockAlignPC(Addr addr)
 155     {
 156         return (addr & ~(cacheBlkMask));
 157     }
 158
 159     /** Returns a specific port. */
 160     Port *getPort(const std::string &if_name, int idx);
 161
 162     /** Read/Write on behalf of an instruction.
 163      *  curResSlot needs to be a valid value in instruction.
 164      */
 165     Fault doDataAccess(DynInstPtr inst);
 166
 167     void prefetch(DynInstPtr inst);
 168
 169     void writeHint(DynInstPtr inst);
 170
 171     uint64_t getMemData(Packet *packet);
 172
 173   protected:
 174     /** Cache interface. */
 175     CachePort *cachePort;
 176
 177     CachePortStatus cacheStatus;
 178
 179     CacheReqPtr retryReq;
 180
 181     PacketPtr retryPkt;
 182
 183     int retrySlot;
 184
 185     bool cacheBlocked;
 186
 187     std::vector<Addr> addrList;
 188
 189     std::map<Addr, InstSeqNum> addrMap;
 190
 191   public:
 192     int cacheBlkSize;
 193
 194     int cacheBlkMask;
 195
 196     /** Align a PC to the start of the Cache block. */
 197     Addr cacheBlockAlign(Addr addr)
 198     {
 199         return (addr & ~(cacheBlkMask));
 200     }
 201
 202     /** The mem line being fetched. */
 203     uint8_t *fetchData[ThePipeline::MaxThreads];
 204
 205     /** @TODO: Move functionaly of fetching more than
 206         one instruction to 'fetch unit'*/
 207     /** The Addr of the cacheline that has been loaded. */
 208     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 209     //unsigned fetchOffset[ThePipeline::MaxThreads];
 210
 211     TheISA::Predecoder predecoder;
 212 };
 213
 214 struct CacheSchedEntry : public ThePipeline::ScheduleEntry
 215 {
 216     enum EntryType {
 217         FetchAccess,
 218         DataAccess
 219     };
 220
 221     CacheSchedEntry(int stage_num, int _priority, int res_num,
 222                     MemCmd::Command pkt_cmd, EntryType _type = FetchAccess)
 223         : ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
 224           type(_type)
 225     { }
 226
 227     MemCmd::Command pktCmd;
 228     EntryType type;
 229 };
 230
 231 class CacheRequest : public ResourceRequest
 232 {
 233   public:
 234     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 235                  int slot_num, unsigned cmd, int req_size,
 236                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
 237         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 238           pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
 239     {
 240         if (cmd == CacheUnit::InitiateFetch ||
 241             cmd == CacheUnit::CompleteFetch ||
 242             cmd == CacheUnit::Fetch) {
 243             memReq = inst->fetchMemReq;
 244         } else {
 245             memReq = inst->dataMemReq;
 246         }
 247
 248         reqData = new uint8_t[req_size];
 249         retryPkt = NULL;
 250     }
 251
 252     virtual ~CacheRequest()
 253     {
 254 #if 0
 255         delete reqData;
 256
 257         // Can get rid of packet and packet request now
 258         if (*dataPkt) {
 259             if (*dataPkt->req) {
 260                 delete dataPkt->req;
 261             }
 262             delete dataPkt;
 263         }
 264
 265         // Can get rid of packet and packet request now
 266         if (retryPkt) {
 267             if (retryPkt->req) {
 268                 delete retryPkt->req;
 269             }
 270             delete retryPkt;
 271         }
 272 #endif
 273     }
 274
 275     virtual PacketDataPtr getData()
 276     {   return reqData; }
 277
 278     void
 279     setMemAccCompleted(bool completed = true)
 280     {
 281         memAccComplete = completed;
 282     }
 283
 284     bool isMemAccComplete() { return memAccComplete; }
 285
 286     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 287     bool isMemAccPending() { return memAccPending; }
 288
 289     //Make this data private/protected!
 290     MemCmd::Command pktCmd;
 291     RequestPtr memReq;
 292     PacketDataPtr reqData;
 293     PacketPtr dataPkt;
 294     PacketPtr retryPkt;
 295
 296     bool memAccComplete;
 297     bool memAccPending;
 298 };
 299
 300 class CacheReqPacket : public Packet
 301 {
 302   public:
 303     CacheReqPacket(CacheRequest *_req,
 304                    Command _cmd, short _dest)
 305         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
 306     {
 307
 308     }
 309
 310     CacheRequest *cacheReq;
 311 };
 312
 313 #endif //__CPU_CACHE_UNIT_HH__