src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47 #include "mem/port.hh"
  48 #include "params/InOrderCPU.hh"
  49 #include "sim/sim_object.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65
  66     enum Command {
  67         InitiateReadData,
  68         CompleteReadData,
  69         InitiateWriteData,
  70         CompleteWriteData,
  71         InitSecondSplitRead,
  72         InitSecondSplitWrite,
  73         CompleteSecondSplitRead,
  74         CompleteSecondSplitWrite
  75     };
  76
  77   public:
  78     /** CachePort class for the Cache Unit.  Handles doing the
  79      * communication with the cache/memory.
  80      */
  81     class CachePort : public Port
  82     {
  83       protected:
  84         /** Pointer to cache port unit */
  85         CacheUnit *cachePortUnit;
  86
  87       public:
  88         /** Default constructor. */
  89         CachePort(CacheUnit *_cachePortUnit)
  90           : Port(_cachePortUnit->name() + "-cache-port",
  91                  (MemObject*)_cachePortUnit->cpu),
  92             cachePortUnit(_cachePortUnit)
  93         { }
  94
  95         bool snoopRangeSent;
  96
  97       protected:
  98         /** Atomic version of receive.  Panics. */
  99         Tick recvAtomic(PacketPtr pkt);
 100
 101         /** Functional version of receive.  Panics. */
 102         void recvFunctional(PacketPtr pkt);
 103
 104         /** Receives status change.  Other than range changing, panics. */
 105         void recvStatusChange(Status status);
 106
 107         /** Returns the address ranges of this device. */
 108         void getDeviceAddressRanges(AddrRangeList &resp,
 109                                             AddrRangeList &snoop)
 110         { resp.clear(); snoop.clear(); }
 111
 112         /** Timing version of receive. Handles setting fetch to the
 113          * proper status to start fetching. */
 114         bool recvTiming(PacketPtr pkt);
 115
 116         /** Handles doing a retry of a failed fetch. */
 117         void recvRetry();
 118     };
 119
 120     void init();
 121
 122     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 123                                 int res_idx, int slot_num,
 124                                 unsigned cmd);
 125
 126     ResReqPtr findRequest(DynInstPtr inst);
 127     ResReqPtr findRequest(DynInstPtr inst, int idx);
 128
 129     void requestAgain(DynInstPtr inst, bool &try_request);
 130
 131     virtual int getSlot(DynInstPtr inst);
 132
 133     /** Executes one of the commands from the "Command" enum */
 134     virtual void execute(int slot_num);
 135
 136     virtual void squash(DynInstPtr inst, int stage_num,
 137                 InstSeqNum squash_seq_num, ThreadID tid);
 138
 139     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 140                              InstSeqNum squash_seq_num, ThreadID tid);
 141
 142     /** After memory request is completedd in the cache, then do final
 143         processing to complete the request in the CPU.
 144     */
 145    virtual void processCacheCompletion(PacketPtr pkt);
 146
 147     void recvRetry();
 148
 149     /** Returns a specific port. */
 150     Port *getPort(const std::string &if_name, int idx);
 151
 152     Fault read(DynInstPtr inst, Addr addr,
 153                uint8_t *data, unsigned size, unsigned flags);
 154
 155     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 156                 Addr addr, unsigned flags, uint64_t *res);
 157
 158     Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 159                       int flags,  TheISA::TLB::Mode tlb_mode);
 160
 161     /** Read/Write on behalf of an instruction.
 162      *  curResSlot needs to be a valid value in instruction.
 163      */
 164     Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
 165                         CacheReqPtr split_req=NULL);
 166
 167     uint64_t getMemData(Packet *packet);
 168
 169     void setAddrDependency(DynInstPtr inst);
 170     void removeAddrDependency(DynInstPtr inst);
 171
 172   protected:
 173     /** Cache interface. */
 174     CachePort *cachePort;
 175
 176     bool cachePortBlocked;
 177
 178     std::vector<Addr> addrList[ThePipeline::MaxThreads];
 179
 180     std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 181
 182   public:
 183     int cacheBlkSize;
 184
 185     int cacheBlkMask;
 186
 187     /** Align a PC to the start of the Cache block. */
 188     Addr cacheBlockAlign(Addr addr)
 189     {
 190         return (addr & ~(cacheBlkMask));
 191     }
 192
 193     TheISA::Predecoder predecoder;
 194
 195     bool tlbBlocked[ThePipeline::MaxThreads];
 196
 197     TheISA::TLB* tlb();
 198
 199     TheISA::TLB *_tlb;
 200 };
 201
 202 class CacheUnitEvent : public ResourceEvent {
 203   public:
 204     const std::string name() const
 205     {
 206         return "CacheUnitEvent";
 207     }
 208
 209
 210     /** Constructs a resource event. */
 211     CacheUnitEvent();
 212     virtual ~CacheUnitEvent() {}
 213
 214     /** Processes a resource event. */
 215     void process();
 216 };
 217
 218 class CacheRequest : public ResourceRequest
 219 {
 220   public:
 221     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 222                  int slot_num, unsigned cmd, int req_size,
 223                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id, int idx)
 224         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 225           pktCmd(pkt_cmd), memReq(NULL), reqData(NULL), dataPkt(NULL),
 226           retryPkt(NULL), memAccComplete(false), memAccPending(false),
 227           tlbStall(false), splitAccess(false), splitAccessNum(-1),
 228           split2ndAccess(false), instIdx(idx)
 229     { }
 230
 231
 232     virtual ~CacheRequest()
 233     {
 234         if (reqData && !splitAccess) {
 235             delete [] reqData;
 236         }
 237     }
 238
 239     virtual PacketDataPtr getData()
 240     { return reqData; }
 241
 242     void
 243     setMemAccCompleted(bool completed = true)
 244     {
 245         memAccComplete = completed;
 246     }
 247
 248     bool is2ndSplit()
 249     {
 250         return split2ndAccess;
 251     }
 252
 253     bool isMemAccComplete() { return memAccComplete; }
 254
 255     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 256     bool isMemAccPending() { return memAccPending; }
 257
 258     //Make this data private/protected!
 259     MemCmd::Command pktCmd;
 260     RequestPtr memReq;
 261     PacketDataPtr reqData;
 262     PacketPtr dataPkt;
 263     PacketPtr retryPkt;
 264
 265     bool memAccComplete;
 266     bool memAccPending;
 267     bool tlbStall;
 268
 269     bool splitAccess;
 270     int splitAccessNum;
 271     bool split2ndAccess;
 272     int instIdx;
 273
 274 };
 275
 276 class CacheReqPacket : public Packet
 277 {
 278   public:
 279     CacheReqPacket(CacheRequest *_req,
 280                    Command _cmd, short _dest, int _idx = 0)
 281         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req), instIdx(_idx)
 282     {
 283
 284     }
 285
 286     CacheRequest *cacheReq;
 287     int instIdx;
 288
 289 };
 290
 291 #endif //__CPU_CACHE_UNIT_HH__