2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
33 #define __CPU_INORDER_CACHE_UNIT_HH__
39 #include "arch/predecoder.hh"
40 #include "arch/tlb.hh"
41 #include "config/the_isa.hh"
42 #include "cpu/inorder/inorder_dyn_inst.hh"
43 #include "cpu/inorder/pipeline_traits.hh"
44 #include "cpu/inorder/resource.hh"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "mem/port.hh"
48 #include "params/InOrderCPU.hh"
49 #include "sim/sim_object.hh"
52 typedef CacheRequest* CacheReqPtr;
55 typedef CacheReqPacket* CacheReqPktPtr;
57 class CacheUnit : public Resource
60 typedef ThePipeline::DynInstPtr DynInstPtr;
63 CacheUnit(std::string res_name, int res_id, int res_width,
64 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
73 CompleteSecondSplitRead,
74 CompleteSecondSplitWrite
78 /** CachePort class for the Cache Unit. Handles doing the
79 * communication with the cache/memory.
81 class CachePort : public Port
84 /** Pointer to cache port unit */
85 CacheUnit *cachePortUnit;
88 /** Default constructor. */
89 CachePort(CacheUnit *_cachePortUnit)
90 : Port(_cachePortUnit->name() + "-cache-port",
91 (MemObject*)_cachePortUnit->cpu),
92 cachePortUnit(_cachePortUnit)
98 /** Atomic version of receive. Panics. */
99 Tick recvAtomic(PacketPtr pkt);
101 /** Functional version of receive. Panics. */
102 void recvFunctional(PacketPtr pkt);
104 /** Receives status change. Other than range changing, panics. */
105 void recvStatusChange(Status status);
107 /** Returns the address ranges of this device. */
108 void getDeviceAddressRanges(AddrRangeList &resp,
109 AddrRangeList &snoop)
110 { resp.clear(); snoop.clear(); }
112 /** Timing version of receive. Handles setting fetch to the
113 * proper status to start fetching. */
114 bool recvTiming(PacketPtr pkt);
116 /** Handles doing a retry of a failed fetch. */
122 ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
123 int res_idx, int slot_num,
126 ResReqPtr findRequest(DynInstPtr inst);
127 ResReqPtr findRequest(DynInstPtr inst, int idx);
129 void requestAgain(DynInstPtr inst, bool &try_request);
131 virtual int getSlot(DynInstPtr inst);
133 /** Executes one of the commands from the "Command" enum */
134 virtual void execute(int slot_num);
136 virtual void squash(DynInstPtr inst, int stage_num,
137 InstSeqNum squash_seq_num, ThreadID tid);
139 void squashDueToMemStall(DynInstPtr inst, int stage_num,
140 InstSeqNum squash_seq_num, ThreadID tid);
142 virtual void squashCacheRequest(CacheReqPtr req_ptr);
144 /** After memory request is completedd in the cache, then do final
145 processing to complete the request in the CPU.
147 virtual void processCacheCompletion(PacketPtr pkt);
149 /** Create request that will interface w/TLB and Memory objects */
150 virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
151 int acc_size, int flags);
153 void finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req);
155 void buildDataPacket(CacheRequest *cache_req);
157 bool processSquash(CacheReqPacket *cache_pkt);
161 /** Returns a specific port. */
162 Port *getPort(const std::string &if_name, int idx);
164 Fault read(DynInstPtr inst, Addr addr,
165 uint8_t *data, unsigned size, unsigned flags);
167 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
168 Addr addr, unsigned flags, uint64_t *res);
170 void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
171 int flags, TheISA::TLB::Mode tlb_mode);
173 /** Read/Write on behalf of an instruction.
174 * curResSlot needs to be a valid value in instruction.
176 void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
177 CacheReqPtr split_req=NULL);
179 uint64_t getMemData(Packet *packet);
181 void setAddrDependency(DynInstPtr inst);
182 virtual void removeAddrDependency(DynInstPtr inst);
185 /** Cache interface. */
186 CachePort *cachePort;
188 bool cachePortBlocked;
190 std::list<Addr> addrList[ThePipeline::MaxThreads];
192 m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
199 /** Align a PC to the start of the Cache block. */
200 Addr cacheBlockAlign(Addr addr)
202 return (addr & ~(cacheBlkMask));
205 bool tlbBlocked[ThePipeline::MaxThreads];
206 InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
212 class CacheUnitEvent : public ResourceEvent {
214 const std::string name() const
216 return "CacheUnitEvent";
220 /** Constructs a resource event. */
222 virtual ~CacheUnitEvent() {}
224 /** Processes a resource event. */
228 //@todo: Move into CacheUnit Class for private access to "valid" field
229 class CacheRequest : public ResourceRequest
232 CacheRequest(CacheUnit *cres)
233 : ResourceRequest(cres), memReq(NULL), reqData(NULL),
234 dataPkt(NULL), memAccComplete(false),
235 memAccPending(false), tlbStall(false), splitAccess(false),
236 splitAccessNum(-1), split2ndAccess(false),
237 fetchBufferFill(false)
240 virtual ~CacheRequest()
242 if (reqData && !splitAccess)
246 void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
247 unsigned _cmd, MemCmd::Command pkt_cmd, int idx)
252 ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
257 virtual PacketDataPtr getData()
261 setMemAccCompleted(bool completed = true)
263 memAccComplete = completed;
268 return split2ndAccess;
271 bool isMemAccComplete() { return memAccComplete; }
273 void setMemAccPending(bool pending = true) { memAccPending = pending; }
274 bool isMemAccPending() { return memAccPending; }
276 //Make this data private/protected!
277 MemCmd::Command pktCmd;
279 PacketDataPtr reqData;
280 CacheReqPacket *dataPkt;
291 /** Should we expect block from cache access or fetch buffer? */
292 bool fetchBufferFill;
295 class CacheReqPacket : public Packet
298 CacheReqPacket(CacheRequest *_req,
299 Command _cmd, short _dest, int _idx = 0)
300 : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
301 instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
306 CacheRequest *cacheReq;
309 PacketDataPtr reqData;
313 #endif //__CPU_CACHE_UNIT_HH__