src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47 #include "mem/port.hh"
  48 #include "params/InOrderCPU.hh"
  49 #include "sim/sim_object.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65
  66     enum Command {
  67         InitiateFetch,
  68         CompleteFetch,
  69         InitiateReadData,
  70         CompleteReadData,
  71         InitiateWriteData,
  72         CompleteWriteData,
  73         Fetch,
  74         ReadData,
  75         WriteData,
  76         InitSecondSplitRead,
  77         InitSecondSplitWrite,
  78         CompleteSecondSplitRead
  79     };
  80
  81   public:
  82     /** CachePort class for the Cache Unit.  Handles doing the
  83      * communication with the cache/memory.
  84      */
  85     class CachePort : public Port
  86     {
  87       protected:
  88         /** Pointer to cache port unit */
  89         CacheUnit *cachePortUnit;
  90
  91       public:
  92         /** Default constructor. */
  93         CachePort(CacheUnit *_cachePortUnit)
  94           : Port(_cachePortUnit->name() + "-cache-port",
  95                  (MemObject*)_cachePortUnit->cpu),
  96             cachePortUnit(_cachePortUnit)
  97         { }
  98
  99         bool snoopRangeSent;
 100
 101       protected:
 102         /** Atomic version of receive.  Panics. */
 103         virtual Tick recvAtomic(PacketPtr pkt);
 104
 105         /** Functional version of receive.  Panics. */
 106         virtual void recvFunctional(PacketPtr pkt);
 107
 108         /** Receives status change.  Other than range changing, panics. */
 109         virtual void recvStatusChange(Status status);
 110
 111         /** Returns the address ranges of this device. */
 112         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 113                                             AddrRangeList &snoop)
 114         { resp.clear(); snoop.clear(); }
 115
 116         /** Timing version of receive. Handles setting fetch to the
 117          * proper status to start fetching. */
 118         virtual bool recvTiming(PacketPtr pkt);
 119
 120         /** Handles doing a retry of a failed fetch. */
 121         virtual void recvRetry();
 122     };
 123
 124     void init();
 125
 126     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 127                                         int res_idx, int slot_num,
 128                                         unsigned cmd);
 129
 130     ResReqPtr findRequest(DynInstPtr inst);
 131     ResReqPtr findSplitRequest(DynInstPtr inst, int idx);
 132
 133     void requestAgain(DynInstPtr inst, bool &try_request);
 134
 135     int getSlot(DynInstPtr inst);
 136
 137     void freeSlot(int slot_num);
 138
 139     /** Execute the function of this resource. The Default is action
 140      *  is to do nothing. More specific models will derive from this
 141      *  class and define their own execute function.
 142      */
 143     void execute(int slot_num);
 144
 145     void squash(DynInstPtr inst, int stage_num,
 146                 InstSeqNum squash_seq_num, ThreadID tid);
 147
 148     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 149                              InstSeqNum squash_seq_num, ThreadID tid);
 150
 151     /** Processes cache completion event. */
 152     void processCacheCompletion(PacketPtr pkt);
 153
 154     void recvRetry();
 155
 156     /** Align a PC to the start of an I-cache block. */
 157     Addr cacheBlockAlignPC(Addr addr)
 158     {
 159         return (addr & ~(cacheBlkMask));
 160     }
 161
 162     /** Returns a specific port. */
 163     Port *getPort(const std::string &if_name, int idx);
 164
 165     template <class T>
 166     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 167
 168     template <class T>
 169     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 170                         uint64_t *res);
 171
 172     Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 173                       int flags,  TheISA::TLB::Mode tlb_mode);
 174
 175     /** Read/Write on behalf of an instruction.
 176      *  curResSlot needs to be a valid value in instruction.
 177      */
 178     Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL, CacheReqPtr split_req=NULL);
 179
 180     void prefetch(DynInstPtr inst);
 181
 182     void writeHint(DynInstPtr inst);
 183
 184     uint64_t getMemData(Packet *packet);
 185
 186   protected:
 187     /** Cache interface. */
 188     CachePort *cachePort;
 189
 190     bool cachePortBlocked;
 191
 192     std::vector<Addr> addrList[ThePipeline::MaxThreads];
 193
 194     std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 195
 196   public:
 197     int cacheBlkSize;
 198
 199     int cacheBlkMask;
 200
 201     /** Align a PC to the start of the Cache block. */
 202     Addr cacheBlockAlign(Addr addr)
 203     {
 204         return (addr & ~(cacheBlkMask));
 205     }
 206
 207     /** The mem line being fetched. */
 208     uint8_t *fetchData[ThePipeline::MaxThreads];
 209
 210     /** @TODO: Move functionaly of fetching more than
 211         one instruction to 'fetch unit'*/
 212     /** The Addr of the cacheline that has been loaded. */
 213     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 214     //unsigned fetchOffset[ThePipeline::MaxThreads];
 215
 216     TheISA::Predecoder predecoder;
 217
 218     bool tlbBlocked[ThePipeline::MaxThreads];
 219
 220     TheISA::TLB* tlb();
 221
 222     TheISA::TLB *_tlb;
 223 };
 224
 225 class CacheUnitEvent : public ResourceEvent {
 226   public:
 227     const std::string name() const
 228     {
 229         return "CacheUnitEvent";
 230     }
 231
 232
 233     /** Constructs a resource event. */
 234     CacheUnitEvent();
 235     virtual ~CacheUnitEvent() {}
 236
 237     /** Processes a resource event. */
 238     virtual void process();
 239 };
 240
 241 class CacheRequest : public ResourceRequest
 242 {
 243   public:
 244     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 245                  int slot_num, unsigned cmd, int req_size,
 246                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id, int idx)
 247         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 248           pktCmd(pkt_cmd), memReq(NULL), reqData(NULL), dataPkt(NULL),
 249           retryPkt(NULL), memAccComplete(false), memAccPending(false),
 250           tlbStall(false), splitAccess(false), splitAccessNum(-1),
 251           split2ndAccess(false), instIdx(idx)
 252     { }
 253
 254
 255     virtual ~CacheRequest()
 256     {
 257         if (reqData && !splitAccess) {
 258             delete [] reqData;
 259         }
 260     }
 261
 262     virtual PacketDataPtr getData()
 263     {   return reqData; }
 264
 265     void
 266     setMemAccCompleted(bool completed = true)
 267     {
 268         memAccComplete = completed;
 269     }
 270
 271     bool is2ndSplit()
 272     {
 273         return split2ndAccess;
 274     }
 275
 276     bool isMemAccComplete() { return memAccComplete; }
 277
 278     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 279     bool isMemAccPending() { return memAccPending; }
 280
 281     //Make this data private/protected!
 282     MemCmd::Command pktCmd;
 283     RequestPtr memReq;
 284     PacketDataPtr reqData;
 285     PacketPtr dataPkt;
 286     PacketPtr retryPkt;
 287
 288     bool memAccComplete;
 289     bool memAccPending;
 290     bool tlbStall;
 291
 292     bool splitAccess;
 293     int splitAccessNum;
 294     bool split2ndAccess;
 295     int instIdx;
 296
 297 };
 298
 299 class CacheReqPacket : public Packet
 300 {
 301   public:
 302     CacheReqPacket(CacheRequest *_req,
 303                    Command _cmd, short _dest, int _idx = 0)
 304         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req), instIdx(_idx)
 305     {
 306
 307     }
 308
 309     CacheRequest *cacheReq;
 310     int instIdx;
 311
 312 };
 313
 314 #endif //__CPU_CACHE_UNIT_HH__