src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47 #include "mem/port.hh"
  48 #include "params/InOrderCPU.hh"
  49 #include "sim/sim_object.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65
  66     enum Command {
  67         InitiateFetch,
  68         CompleteFetch,
  69         InitiateReadData,
  70         CompleteReadData,
  71         InitiateWriteData,
  72         CompleteWriteData,
  73         Fetch,
  74         ReadData,
  75         WriteData,
  76         InitSecondSplitRead,
  77         InitSecondSplitWrite,
  78         CompleteSecondSplitRead,
  79         CompleteSecondSplitWrite
  80     };
  81
  82   public:
  83     /** CachePort class for the Cache Unit.  Handles doing the
  84      * communication with the cache/memory.
  85      */
  86     class CachePort : public Port
  87     {
  88       protected:
  89         /** Pointer to cache port unit */
  90         CacheUnit *cachePortUnit;
  91
  92       public:
  93         /** Default constructor. */
  94         CachePort(CacheUnit *_cachePortUnit)
  95           : Port(_cachePortUnit->name() + "-cache-port",
  96                  (MemObject*)_cachePortUnit->cpu),
  97             cachePortUnit(_cachePortUnit)
  98         { }
  99
 100         bool snoopRangeSent;
 101
 102       protected:
 103         /** Atomic version of receive.  Panics. */
 104         Tick recvAtomic(PacketPtr pkt);
 105
 106         /** Functional version of receive.  Panics. */
 107         void recvFunctional(PacketPtr pkt);
 108
 109         /** Receives status change.  Other than range changing, panics. */
 110         void recvStatusChange(Status status);
 111
 112         /** Returns the address ranges of this device. */
 113         void getDeviceAddressRanges(AddrRangeList &resp,
 114                                             AddrRangeList &snoop)
 115         { resp.clear(); snoop.clear(); }
 116
 117         /** Timing version of receive. Handles setting fetch to the
 118          * proper status to start fetching. */
 119         bool recvTiming(PacketPtr pkt);
 120
 121         /** Handles doing a retry of a failed fetch. */
 122         void recvRetry();
 123     };
 124
 125     void init();
 126
 127     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 128                                         int res_idx, int slot_num,
 129                                         unsigned cmd);
 130
 131     ResReqPtr findRequest(DynInstPtr inst);
 132     ResReqPtr findSplitRequest(DynInstPtr inst, int idx);
 133
 134     void requestAgain(DynInstPtr inst, bool &try_request);
 135
 136     int getSlot(DynInstPtr inst);
 137
 138     /** Execute the function of this resource. The Default is action
 139      *  is to do nothing. More specific models will derive from this
 140      *  class and define their own execute function.
 141      */
 142     void execute(int slot_num);
 143
 144     void squash(DynInstPtr inst, int stage_num,
 145                 InstSeqNum squash_seq_num, ThreadID tid);
 146
 147     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 148                              InstSeqNum squash_seq_num, ThreadID tid);
 149
 150     /** Processes cache completion event. */
 151     void processCacheCompletion(PacketPtr pkt);
 152
 153     void recvRetry();
 154
 155     /** Align a PC to the start of an I-cache block. */
 156     Addr cacheBlockAlignPC(Addr addr)
 157     {
 158         return (addr & ~(cacheBlkMask));
 159     }
 160
 161     /** Returns a specific port. */
 162     Port *getPort(const std::string &if_name, int idx);
 163
 164     Fault read(DynInstPtr inst, Addr addr,
 165                uint8_t *data, unsigned size, unsigned flags);
 166
 167     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 168                 Addr addr, unsigned flags, uint64_t *res);
 169
 170     Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 171                       int flags,  TheISA::TLB::Mode tlb_mode);
 172
 173     /** Read/Write on behalf of an instruction.
 174      *  curResSlot needs to be a valid value in instruction.
 175      */
 176     Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
 177                         CacheReqPtr split_req=NULL);
 178
 179     void prefetch(DynInstPtr inst);
 180
 181     void writeHint(DynInstPtr inst);
 182
 183     uint64_t getMemData(Packet *packet);
 184
 185     void setAddrDependency(DynInstPtr inst);
 186     void removeAddrDependency(DynInstPtr inst);
 187
 188   protected:
 189     /** Cache interface. */
 190     CachePort *cachePort;
 191
 192     bool cachePortBlocked;
 193
 194     std::vector<Addr> addrList[ThePipeline::MaxThreads];
 195
 196     std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 197
 198   public:
 199     int cacheBlkSize;
 200
 201     int cacheBlkMask;
 202
 203     /** Align a PC to the start of the Cache block. */
 204     Addr cacheBlockAlign(Addr addr)
 205     {
 206         return (addr & ~(cacheBlkMask));
 207     }
 208
 209     /** The mem line being fetched. */
 210     uint8_t *fetchData[ThePipeline::MaxThreads];
 211
 212     /** @TODO: Move functionaly of fetching more than
 213         one instruction to 'fetch unit'*/
 214     /** The Addr of the cacheline that has been loaded. */
 215     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 216     //unsigned fetchOffset[ThePipeline::MaxThreads];
 217
 218     TheISA::Predecoder predecoder;
 219
 220     bool tlbBlocked[ThePipeline::MaxThreads];
 221
 222     TheISA::TLB* tlb();
 223
 224     TheISA::TLB *_tlb;
 225 };
 226
 227 class CacheUnitEvent : public ResourceEvent {
 228   public:
 229     const std::string name() const
 230     {
 231         return "CacheUnitEvent";
 232     }
 233
 234
 235     /** Constructs a resource event. */
 236     CacheUnitEvent();
 237     virtual ~CacheUnitEvent() {}
 238
 239     /** Processes a resource event. */
 240     void process();
 241 };
 242
 243 class CacheRequest : public ResourceRequest
 244 {
 245   public:
 246     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 247                  int slot_num, unsigned cmd, int req_size,
 248                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id, int idx)
 249         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 250           pktCmd(pkt_cmd), memReq(NULL), reqData(NULL), dataPkt(NULL),
 251           retryPkt(NULL), memAccComplete(false), memAccPending(false),
 252           tlbStall(false), splitAccess(false), splitAccessNum(-1),
 253           split2ndAccess(false), instIdx(idx)
 254     { }
 255
 256
 257     virtual ~CacheRequest()
 258     {
 259         if (reqData && !splitAccess) {
 260             delete [] reqData;
 261         }
 262     }
 263
 264     virtual PacketDataPtr getData()
 265     {   return reqData; }
 266
 267     void
 268     setMemAccCompleted(bool completed = true)
 269     {
 270         memAccComplete = completed;
 271     }
 272
 273     bool is2ndSplit()
 274     {
 275         return split2ndAccess;
 276     }
 277
 278     bool isMemAccComplete() { return memAccComplete; }
 279
 280     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 281     bool isMemAccPending() { return memAccPending; }
 282
 283     //Make this data private/protected!
 284     MemCmd::Command pktCmd;
 285     RequestPtr memReq;
 286     PacketDataPtr reqData;
 287     PacketPtr dataPkt;
 288     PacketPtr retryPkt;
 289
 290     bool memAccComplete;
 291     bool memAccPending;
 292     bool tlbStall;
 293
 294     bool splitAccess;
 295     int splitAccessNum;
 296     bool split2ndAccess;
 297     int instIdx;
 298
 299 };
 300
 301 class CacheReqPacket : public Packet
 302 {
 303   public:
 304     CacheReqPacket(CacheRequest *_req,
 305                    Command _cmd, short _dest, int _idx = 0)
 306         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req), instIdx(_idx)
 307     {
 308
 309     }
 310
 311     CacheRequest *cacheReq;
 312     int instIdx;
 313
 314 };
 315
 316 #endif //__CPU_CACHE_UNIT_HH__