src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 //#include "cpu/inorder/params.hh"
  40
  41 #include "cpu/inorder/resource.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "mem/packet.hh"
  44 #include "mem/packet_access.hh"
  45 #include "mem/port.hh"
  46 #include "cpu/inorder/pipeline_traits.hh"
  47 #include "sim/sim_object.hh"
  48
  49 #include "params/InOrderCPU.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource {
  58   public:
  59     typedef ThePipeline::DynInstPtr DynInstPtr;
  60
  61   public:
  62     CacheUnit(std::string res_name, int res_id, int res_width,
  63               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  64     virtual ~CacheUnit() {}
  65
  66     enum Command {
  67         InitiateFetch,
  68         CompleteFetch,
  69         InitiateReadData,
  70         CompleteReadData,
  71         InitiateWriteData,
  72         CompleteWriteData,
  73         Fetch,
  74         ReadData,
  75         WriteData
  76     };
  77
  78   public:
  79     /** CachePort class for the Cache Unit.  Handles doing the
  80      * communication with the cache/memory.
  81      */
  82     class CachePort : public Port
  83     {
  84       protected:
  85         /** Pointer to cache port unit */
  86         CacheUnit *cachePortUnit;
  87
  88       public:
  89         /** Default constructor. */
  90         CachePort(CacheUnit *_cachePortUnit)
  91           : Port(_cachePortUnit->name() + "-cache-port", (MemObject*)_cachePortUnit->cpu),
  92               cachePortUnit(_cachePortUnit)
  93         { }
  94
  95         bool snoopRangeSent;
  96
  97       protected:
  98         /** Atomic version of receive.  Panics. */
  99         virtual Tick recvAtomic(PacketPtr pkt);
 100
 101         /** Functional version of receive.  Panics. */
 102         virtual void recvFunctional(PacketPtr pkt);
 103
 104         /** Receives status change.  Other than range changing, panics. */
 105         virtual void recvStatusChange(Status status);
 106
 107         /** Returns the address ranges of this device. */
 108         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 109                                             AddrRangeList &snoop)
 110         { resp.clear(); snoop.clear(); }
 111
 112         /** Timing version of receive. Handles setting fetch to the
 113          * proper status to start fetching. */
 114         virtual bool recvTiming(PacketPtr pkt);
 115
 116         /** Handles doing a retry of a failed fetch. */
 117         virtual void recvRetry();
 118     };
 119
 120     enum CachePortStatus {
 121         cacheWaitResponse,
 122         cacheWaitRetry,
 123         cacheAccessComplete
 124     };
 125
 126     ///virtual void init();
 127
 128     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 129                                         int res_idx, int slot_num,
 130                                         unsigned cmd);
 131
 132     void requestAgain(DynInstPtr inst, bool &try_request);
 133
 134     int getSlot(DynInstPtr inst);
 135
 136     void freeSlot(int slot_num);
 137
 138     /** Execute the function of this resource. The Default is action
 139      *  is to do nothing. More specific models will derive from this
 140      *  class and define their own execute function.
 141      */
 142     void execute(int slot_num);
 143
 144     void squash(DynInstPtr inst, int stage_num,
 145                 InstSeqNum squash_seq_num, unsigned tid);
 146
 147     /** Processes cache completion event. */
 148     void processCacheCompletion(PacketPtr pkt);
 149
 150     void recvRetry();
 151
 152     /** Align a PC to the start of an I-cache block. */
 153     Addr cacheBlockAlignPC(Addr addr)
 154     {
 155         //addr = TheISA::realPCToFetchPC(addr);
 156         return (addr & ~(cacheBlkMask));
 157     }
 158
 159     /** Returns a specific port. */
 160     Port *getPort(const std::string &if_name, int idx);
 161
 162     /** Fetch on behalf of an instruction. Will check to see
 163      *  if instruction is actually in resource before
 164      *  trying to fetch.
 165      */
 166     //Fault doFetchAccess(DynInstPtr inst);
 167
 168     /** Read/Write on behalf of an instruction.
 169      *  curResSlot needs to be a valid value in instruction.
 170      */
 171     Fault doDataAccess(DynInstPtr inst);
 172
 173     uint64_t getMemData(Packet *packet);
 174
 175   protected:
 176     /** Cache interface. */
 177     CachePort *cachePort;
 178
 179     CachePortStatus cacheStatus;
 180
 181     CacheReqPtr retryReq;
 182
 183     PacketPtr retryPkt;
 184
 185     int retrySlot;
 186
 187     bool cacheBlocked;
 188
 189     std::vector<Addr> addrList;
 190
 191     std::map<Addr, InstSeqNum> addrMap;
 192
 193   public:
 194     int cacheBlkSize;
 195
 196     int cacheBlkMask;
 197
 198     /** Align a PC to the start of the Cache block. */
 199     Addr cacheBlockAlign(Addr addr)
 200     {
 201         return (addr & ~(cacheBlkMask));
 202     }
 203
 204     /** THINGS USED FOR FETCH */
 205     // NO LONGER USED BY COMMENT OUT UNTIL FULL VERIFICATION
 206     /** The mem line being fetched. */
 207     //uint8_t *cacheData[ThePipeline::MaxThreads];
 208
 209     /** The Addr of the cacheline that has been loaded. */
 210     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 211
 212     //unsigned fetchOffset[ThePipeline::MaxThreads];
 213
 214     /** @todo: Add Resource Stats Here */
 215 };
 216
 217 struct CacheSchedEntry : public ThePipeline::ScheduleEntry {
 218     enum EntryType {
 219         FetchAccess,
 220         DataAccess
 221     };
 222
 223     CacheSchedEntry(int stage_num, int _priority, int res_num, MemCmd::Command pkt_cmd,
 224                     EntryType _type = FetchAccess) :
 225         ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
 226         type(_type)
 227     { }
 228
 229     MemCmd::Command pktCmd;
 230     EntryType type;
 231 };
 232
 233 class CacheRequest : public ResourceRequest {
 234   public:
 235     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 236                  int slot_num, unsigned cmd, int req_size,
 237                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
 238         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 239           pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
 240     {
 241         memReq = inst->memReq;
 242
 243         reqData = new uint8_t[req_size];
 244         retryPkt = NULL;
 245     }
 246
 247     virtual ~CacheRequest()
 248     {
 249         /*
 250         delete reqData;
 251
 252         Can get rid of packet and packet request now
 253         if (*dataPkt) {
 254             if (*dataPkt->req) {
 255                 delete dataPkt->req;
 256             }
 257             delete dataPkt;
 258         }
 259
 260         // Can get rid of packet and packet request now
 261         if (retryPkt) {
 262             if (retryPkt->req) {
 263                 delete retryPkt->req;
 264             }
 265             delete retryPkt;
 266             }*/
 267
 268         if (memReq) {
 269             delete memReq;
 270         }
 271     }
 272
 273     virtual PacketDataPtr getData()
 274     {   return reqData; }
 275
 276     void setMemAccCompleted(bool completed = true) { memAccComplete = completed; }
 277     bool isMemAccComplete() { return memAccComplete; }
 278
 279     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 280     bool isMemAccPending() { return memAccPending; }
 281
 282     //Make this data private/protected!
 283     MemCmd::Command pktCmd;
 284     RequestPtr memReq;
 285     PacketDataPtr reqData;
 286     PacketPtr dataPkt;
 287     PacketPtr retryPkt;
 288
 289     bool memAccComplete;
 290     bool memAccPending;
 291 };
 292
 293 class CacheReqPacket : public Packet {
 294   public:
 295     CacheReqPacket(CacheRequest *_req,
 296                    Command _cmd, short _dest)
 297         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
 298     {
 299
 300     }
 301
 302     CacheRequest *cacheReq;
 303 };
 304
 305 #endif //__CPU_CACHE_UNIT_HH__