src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 //#include "cpu/inorder/params.hh"
  40
  41 #include "cpu/inorder/resource.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "mem/packet.hh"
  44 #include "mem/packet_access.hh"
  45 #include "mem/port.hh"
  46 #include "cpu/inorder/pipeline_traits.hh"
  47 #include "sim/sim_object.hh"
  48
  49 #include "params/InOrderCPU.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65     virtual ~CacheUnit() {}
  66
  67     enum Command {
  68         InitiateFetch,
  69         CompleteFetch,
  70         InitiateReadData,
  71         CompleteReadData,
  72         InitiateWriteData,
  73         CompleteWriteData,
  74         Fetch,
  75         ReadData,
  76         WriteData
  77     };
  78
  79   public:
  80     /** CachePort class for the Cache Unit.  Handles doing the
  81      * communication with the cache/memory.
  82      */
  83     class CachePort : public Port
  84     {
  85       protected:
  86         /** Pointer to cache port unit */
  87         CacheUnit *cachePortUnit;
  88
  89       public:
  90         /** Default constructor. */
  91         CachePort(CacheUnit *_cachePortUnit)
  92           : Port(_cachePortUnit->name() + "-cache-port",
  93                  (MemObject*)_cachePortUnit->cpu),
  94             cachePortUnit(_cachePortUnit)
  95         { }
  96
  97         bool snoopRangeSent;
  98
  99       protected:
 100         /** Atomic version of receive.  Panics. */
 101         virtual Tick recvAtomic(PacketPtr pkt);
 102
 103         /** Functional version of receive.  Panics. */
 104         virtual void recvFunctional(PacketPtr pkt);
 105
 106         /** Receives status change.  Other than range changing, panics. */
 107         virtual void recvStatusChange(Status status);
 108
 109         /** Returns the address ranges of this device. */
 110         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 111                                             AddrRangeList &snoop)
 112         { resp.clear(); snoop.clear(); }
 113
 114         /** Timing version of receive. Handles setting fetch to the
 115          * proper status to start fetching. */
 116         virtual bool recvTiming(PacketPtr pkt);
 117
 118         /** Handles doing a retry of a failed fetch. */
 119         virtual void recvRetry();
 120     };
 121
 122     enum CachePortStatus {
 123         cacheWaitResponse,
 124         cacheWaitRetry,
 125         cacheAccessComplete
 126     };
 127
 128     ///virtual void init();
 129
 130     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 131                                         int res_idx, int slot_num,
 132                                         unsigned cmd);
 133
 134     void requestAgain(DynInstPtr inst, bool &try_request);
 135
 136     int getSlot(DynInstPtr inst);
 137
 138     void freeSlot(int slot_num);
 139
 140     /** Execute the function of this resource. The Default is action
 141      *  is to do nothing. More specific models will derive from this
 142      *  class and define their own execute function.
 143      */
 144     void execute(int slot_num);
 145
 146     void squash(DynInstPtr inst, int stage_num,
 147                 InstSeqNum squash_seq_num, unsigned tid);
 148
 149     /** Processes cache completion event. */
 150     void processCacheCompletion(PacketPtr pkt);
 151
 152     void recvRetry();
 153
 154     /** Align a PC to the start of an I-cache block. */
 155     Addr cacheBlockAlignPC(Addr addr)
 156     {
 157         //addr = TheISA::realPCToFetchPC(addr);
 158         return (addr & ~(cacheBlkMask));
 159     }
 160
 161     /** Returns a specific port. */
 162     Port *getPort(const std::string &if_name, int idx);
 163
 164     /** Fetch on behalf of an instruction. Will check to see
 165      *  if instruction is actually in resource before
 166      *  trying to fetch.
 167      */
 168     //Fault doFetchAccess(DynInstPtr inst);
 169
 170     /** Read/Write on behalf of an instruction.
 171      *  curResSlot needs to be a valid value in instruction.
 172      */
 173     Fault doDataAccess(DynInstPtr inst);
 174
 175     uint64_t getMemData(Packet *packet);
 176
 177   protected:
 178     /** Cache interface. */
 179     CachePort *cachePort;
 180
 181     CachePortStatus cacheStatus;
 182
 183     CacheReqPtr retryReq;
 184
 185     PacketPtr retryPkt;
 186
 187     int retrySlot;
 188
 189     bool cacheBlocked;
 190
 191     std::vector<Addr> addrList;
 192
 193     std::map<Addr, InstSeqNum> addrMap;
 194
 195   public:
 196     int cacheBlkSize;
 197
 198     int cacheBlkMask;
 199
 200     /** Align a PC to the start of the Cache block. */
 201     Addr cacheBlockAlign(Addr addr)
 202     {
 203         return (addr & ~(cacheBlkMask));
 204     }
 205
 206     /** THINGS USED FOR FETCH */
 207     // NO LONGER USED BY COMMENT OUT UNTIL FULL VERIFICATION
 208     /** The mem line being fetched. */
 209     //uint8_t *cacheData[ThePipeline::MaxThreads];
 210
 211     /** The Addr of the cacheline that has been loaded. */
 212     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 213
 214     //unsigned fetchOffset[ThePipeline::MaxThreads];
 215
 216     /** @todo: Add Resource Stats Here */
 217 };
 218
 219 struct CacheSchedEntry : public ThePipeline::ScheduleEntry
 220 {
 221     enum EntryType {
 222         FetchAccess,
 223         DataAccess
 224     };
 225
 226     CacheSchedEntry(int stage_num, int _priority, int res_num,
 227                     MemCmd::Command pkt_cmd, EntryType _type = FetchAccess)
 228         : ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
 229           type(_type)
 230     { }
 231
 232     MemCmd::Command pktCmd;
 233     EntryType type;
 234 };
 235
 236 class CacheRequest : public ResourceRequest
 237 {
 238   public:
 239     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 240                  int slot_num, unsigned cmd, int req_size,
 241                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
 242         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 243           pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
 244     {
 245         memReq = inst->memReq;
 246
 247         reqData = new uint8_t[req_size];
 248         retryPkt = NULL;
 249     }
 250
 251     virtual ~CacheRequest()
 252     {
 253 #if 0
 254         delete reqData;
 255
 256         // Can get rid of packet and packet request now
 257         if (*dataPkt) {
 258             if (*dataPkt->req) {
 259                 delete dataPkt->req;
 260             }
 261             delete dataPkt;
 262         }
 263
 264         // Can get rid of packet and packet request now
 265         if (retryPkt) {
 266             if (retryPkt->req) {
 267                 delete retryPkt->req;
 268             }
 269             delete retryPkt;
 270         }
 271 #endif
 272
 273         if (memReq)
 274             delete memReq;
 275     }
 276
 277     virtual PacketDataPtr getData()
 278     {   return reqData; }
 279
 280     void
 281     setMemAccCompleted(bool completed = true)
 282     {
 283         memAccComplete = completed;
 284     }
 285
 286     bool isMemAccComplete() { return memAccComplete; }
 287
 288     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 289     bool isMemAccPending() { return memAccPending; }
 290
 291     //Make this data private/protected!
 292     MemCmd::Command pktCmd;
 293     RequestPtr memReq;
 294     PacketDataPtr reqData;
 295     PacketPtr dataPkt;
 296     PacketPtr retryPkt;
 297
 298     bool memAccComplete;
 299     bool memAccPending;
 300 };
 301
 302 class CacheReqPacket : public Packet
 303 {
 304   public:
 305     CacheReqPacket(CacheRequest *_req,
 306                    Command _cmd, short _dest)
 307         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
 308     {
 309
 310     }
 311
 312     CacheRequest *cacheReq;
 313 };
 314
 315 #endif //__CPU_CACHE_UNIT_HH__