src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47 #include "mem/port.hh"
  48 #include "params/InOrderCPU.hh"
  49 #include "sim/sim_object.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65
  66     enum Command {
  67         InitiateReadData,
  68         CompleteReadData,
  69         InitiateWriteData,
  70         CompleteWriteData,
  71         InitSecondSplitRead,
  72         InitSecondSplitWrite,
  73         CompleteSecondSplitRead,
  74         CompleteSecondSplitWrite
  75     };
  76
  77   public:
  78     /** CachePort class for the Cache Unit.  Handles doing the
  79      * communication with the cache/memory.
  80      */
  81     class CachePort : public Port
  82     {
  83       protected:
  84         /** Pointer to cache port unit */
  85         CacheUnit *cachePortUnit;
  86
  87       public:
  88         /** Default constructor. */
  89         CachePort(CacheUnit *_cachePortUnit)
  90           : Port(_cachePortUnit->name() + "-cache-port",
  91                  (MemObject*)_cachePortUnit->cpu),
  92             cachePortUnit(_cachePortUnit)
  93         { }
  94
  95         bool snoopRangeSent;
  96
  97       protected:
  98         /** Atomic version of receive.  Panics. */
  99         Tick recvAtomic(PacketPtr pkt);
 100
 101         /** Functional version of receive.  Panics. */
 102         void recvFunctional(PacketPtr pkt);
 103
 104         /** Receives status change.  Other than range changing, panics. */
 105         void recvStatusChange(Status status);
 106
 107         /** Returns the address ranges of this device. */
 108         void getDeviceAddressRanges(AddrRangeList &resp,
 109                                             AddrRangeList &snoop)
 110         { resp.clear(); snoop.clear(); }
 111
 112         /** Timing version of receive. Handles setting fetch to the
 113          * proper status to start fetching. */
 114         bool recvTiming(PacketPtr pkt);
 115
 116         /** Handles doing a retry of a failed fetch. */
 117         void recvRetry();
 118     };
 119
 120     void init();
 121
 122     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 123                                 int res_idx, int slot_num,
 124                                 unsigned cmd);
 125
 126     ResReqPtr findRequest(DynInstPtr inst);
 127     ResReqPtr findRequest(DynInstPtr inst, int idx);
 128
 129     void requestAgain(DynInstPtr inst, bool &try_request);
 130
 131     virtual int getSlot(DynInstPtr inst);
 132
 133     /** Executes one of the commands from the "Command" enum */
 134     virtual void execute(int slot_num);
 135
 136     virtual void squash(DynInstPtr inst, int stage_num,
 137                 InstSeqNum squash_seq_num, ThreadID tid);
 138
 139     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 140                              InstSeqNum squash_seq_num, ThreadID tid);
 141
 142     virtual void squashCacheRequest(CacheReqPtr req_ptr);
 143
 144     /** After memory request is completedd in the cache, then do final
 145         processing to complete the request in the CPU.
 146     */
 147     virtual void processCacheCompletion(PacketPtr pkt);
 148
 149     /** Create request that will interface w/TLB and Memory objects */
 150     virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 151                                  int acc_size, int flags);
 152
 153     void recvRetry();
 154
 155     /** Returns a specific port. */
 156     Port *getPort(const std::string &if_name, int idx);
 157
 158     Fault read(DynInstPtr inst, Addr addr,
 159                uint8_t *data, unsigned size, unsigned flags);
 160
 161     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 162                 Addr addr, unsigned flags, uint64_t *res);
 163
 164     void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 165                       int flags,  TheISA::TLB::Mode tlb_mode);
 166
 167     /** Read/Write on behalf of an instruction.
 168      *  curResSlot needs to be a valid value in instruction.
 169      */
 170     void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
 171                         CacheReqPtr split_req=NULL);
 172
 173     uint64_t getMemData(Packet *packet);
 174
 175     void setAddrDependency(DynInstPtr inst);
 176     virtual void removeAddrDependency(DynInstPtr inst);
 177
 178   protected:
 179     /** Cache interface. */
 180     CachePort *cachePort;
 181
 182     bool cachePortBlocked;
 183
 184     std::vector<Addr> addrList[ThePipeline::MaxThreads];
 185
 186     std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 187
 188   public:
 189     int cacheBlkSize;
 190
 191     int cacheBlkMask;
 192
 193     /** Align a PC to the start of the Cache block. */
 194     Addr cacheBlockAlign(Addr addr)
 195     {
 196         return (addr & ~(cacheBlkMask));
 197     }
 198
 199     bool tlbBlocked[ThePipeline::MaxThreads];
 200
 201     TheISA::TLB* tlb();
 202
 203     TheISA::TLB *_tlb;
 204 };
 205
 206 class CacheUnitEvent : public ResourceEvent {
 207   public:
 208     const std::string name() const
 209     {
 210         return "CacheUnitEvent";
 211     }
 212
 213
 214     /** Constructs a resource event. */
 215     CacheUnitEvent();
 216     virtual ~CacheUnitEvent() {}
 217
 218     /** Processes a resource event. */
 219     void process();
 220 };
 221
 222 //@todo: Move into CacheUnit Class for private access to "valid" field
 223 class CacheRequest : public ResourceRequest
 224 {
 225   public:
 226     CacheRequest(CacheUnit *cres)
 227         :  ResourceRequest(cres), memReq(NULL), reqData(NULL),
 228            dataPkt(NULL), retryPkt(NULL), memAccComplete(false),
 229            memAccPending(false), tlbStall(false), splitAccess(false),
 230            splitAccessNum(-1), split2ndAccess(false),
 231            fetchBufferFill(false)
 232     { }
 233
 234     virtual ~CacheRequest()
 235     {
 236         if (reqData && !splitAccess) {
 237             delete [] reqData;
 238         }
 239     }
 240
 241     void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
 242                     unsigned _cmd, MemCmd::Command pkt_cmd, int idx)
 243     {
 244         pktCmd = pkt_cmd;
 245         instIdx = idx;
 246
 247         ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
 248     }
 249
 250     void clearRequest()
 251     {
 252         memReq = NULL;
 253         reqData = NULL;
 254         dataPkt = NULL;
 255         retryPkt = NULL;
 256         memAccComplete = false;
 257         memAccPending = false;
 258         tlbStall = false;
 259         splitAccess = false;
 260         splitAccessNum = -1;
 261         split2ndAccess = false;
 262         instIdx = 0;
 263         fetchBufferFill = false;
 264
 265         ResourceRequest::clearRequest();
 266     }
 267
 268     virtual PacketDataPtr getData()
 269     { return reqData; }
 270
 271     void
 272     setMemAccCompleted(bool completed = true)
 273     {
 274         memAccComplete = completed;
 275     }
 276
 277     bool is2ndSplit()
 278     {
 279         return split2ndAccess;
 280     }
 281
 282     bool isMemAccComplete() { return memAccComplete; }
 283
 284     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 285     bool isMemAccPending() { return memAccPending; }
 286
 287     //Make this data private/protected!
 288     MemCmd::Command pktCmd;
 289     RequestPtr memReq;
 290     PacketDataPtr reqData;
 291     PacketPtr dataPkt;
 292     PacketPtr retryPkt;
 293
 294     bool memAccComplete;
 295     bool memAccPending;
 296     bool tlbStall;
 297
 298     bool splitAccess;
 299     int splitAccessNum;
 300     bool split2ndAccess;
 301     int instIdx;
 302
 303     /** Should we expect block from cache access or fetch buffer? */
 304     bool fetchBufferFill;
 305 };
 306
 307 class CacheReqPacket : public Packet
 308 {
 309   public:
 310     CacheReqPacket(CacheRequest *_req,
 311                    Command _cmd, short _dest, int _idx = 0)
 312         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req), instIdx(_idx)
 313     {
 314
 315     }
 316
 317     CacheRequest *cacheReq;
 318     int instIdx;
 319
 320 };
 321
 322 #endif //__CPU_CACHE_UNIT_HH__