src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/tlb.hh"
  40 #include "arch/predecoder.hh"
  41 #include "cpu/inorder/resource.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "mem/packet.hh"
  44 #include "mem/packet_access.hh"
  45 #include "mem/port.hh"
  46 #include "cpu/inorder/pipeline_traits.hh"
  47 #include "sim/sim_object.hh"
  48
  49 #include "params/InOrderCPU.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65     virtual ~CacheUnit() {}
  66
  67     enum Command {
  68         InitiateFetch,
  69         CompleteFetch,
  70         InitiateReadData,
  71         CompleteReadData,
  72         InitiateWriteData,
  73         CompleteWriteData,
  74         Fetch,
  75         ReadData,
  76         WriteData
  77     };
  78
  79   public:
  80     /** CachePort class for the Cache Unit.  Handles doing the
  81      * communication with the cache/memory.
  82      */
  83     class CachePort : public Port
  84     {
  85       protected:
  86         /** Pointer to cache port unit */
  87         CacheUnit *cachePortUnit;
  88
  89       public:
  90         /** Default constructor. */
  91         CachePort(CacheUnit *_cachePortUnit)
  92           : Port(_cachePortUnit->name() + "-cache-port",
  93                  (MemObject*)_cachePortUnit->cpu),
  94             cachePortUnit(_cachePortUnit)
  95         { }
  96
  97         bool snoopRangeSent;
  98
  99       protected:
 100         /** Atomic version of receive.  Panics. */
 101         virtual Tick recvAtomic(PacketPtr pkt);
 102
 103         /** Functional version of receive.  Panics. */
 104         virtual void recvFunctional(PacketPtr pkt);
 105
 106         /** Receives status change.  Other than range changing, panics. */
 107         virtual void recvStatusChange(Status status);
 108
 109         /** Returns the address ranges of this device. */
 110         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 111                                             AddrRangeList &snoop)
 112         { resp.clear(); snoop.clear(); }
 113
 114         /** Timing version of receive. Handles setting fetch to the
 115          * proper status to start fetching. */
 116         virtual bool recvTiming(PacketPtr pkt);
 117
 118         /** Handles doing a retry of a failed fetch. */
 119         virtual void recvRetry();
 120     };
 121
 122     enum CachePortStatus {
 123         cacheWaitResponse,
 124         cacheWaitRetry,
 125         cacheAccessComplete
 126     };
 127
 128     void init();
 129
 130     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 131                                         int res_idx, int slot_num,
 132                                         unsigned cmd);
 133
 134     void requestAgain(DynInstPtr inst, bool &try_request);
 135
 136     int getSlot(DynInstPtr inst);
 137
 138     void freeSlot(int slot_num);
 139
 140     /** Execute the function of this resource. The Default is action
 141      *  is to do nothing. More specific models will derive from this
 142      *  class and define their own execute function.
 143      */
 144     void execute(int slot_num);
 145
 146     void squash(DynInstPtr inst, int stage_num,
 147                 InstSeqNum squash_seq_num, unsigned tid);
 148
 149     /** Processes cache completion event. */
 150     void processCacheCompletion(PacketPtr pkt);
 151
 152     void recvRetry();
 153
 154     /** Align a PC to the start of an I-cache block. */
 155     Addr cacheBlockAlignPC(Addr addr)
 156     {
 157         return (addr & ~(cacheBlkMask));
 158     }
 159
 160     /** Returns a specific port. */
 161     Port *getPort(const std::string &if_name, int idx);
 162
 163     template <class T>
 164     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 165
 166     template <class T>
 167     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 168                         uint64_t *res);
 169
 170     Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 171                       int flags,  TheISA::TLB::Mode tlb_mode);
 172
 173     /** Read/Write on behalf of an instruction.
 174      *  curResSlot needs to be a valid value in instruction.
 175      */
 176     Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL);
 177
 178     void prefetch(DynInstPtr inst);
 179
 180     void writeHint(DynInstPtr inst);
 181
 182     uint64_t getMemData(Packet *packet);
 183
 184   protected:
 185     /** Cache interface. */
 186     CachePort *cachePort;
 187
 188     CachePortStatus cacheStatus;
 189
 190     CacheReqPtr retryReq;
 191
 192     PacketPtr retryPkt;
 193
 194     int retrySlot;
 195
 196     bool cacheBlocked;
 197
 198     std::vector<Addr> addrList;
 199
 200     std::map<Addr, InstSeqNum> addrMap;
 201
 202   public:
 203     int cacheBlkSize;
 204
 205     int cacheBlkMask;
 206
 207     /** Align a PC to the start of the Cache block. */
 208     Addr cacheBlockAlign(Addr addr)
 209     {
 210         return (addr & ~(cacheBlkMask));
 211     }
 212
 213     /** The mem line being fetched. */
 214     uint8_t *fetchData[ThePipeline::MaxThreads];
 215
 216     /** @TODO: Move functionaly of fetching more than
 217         one instruction to 'fetch unit'*/
 218     /** The Addr of the cacheline that has been loaded. */
 219     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 220     //unsigned fetchOffset[ThePipeline::MaxThreads];
 221
 222     TheISA::Predecoder predecoder;
 223
 224     bool tlbBlocked[ThePipeline::MaxThreads];
 225
 226     TheISA::TLB* tlb();
 227
 228     TheISA::TLB *_tlb;
 229 };
 230
 231 class CacheUnitEvent : public ResourceEvent {
 232   public:
 233     const std::string name() const
 234     {
 235         return "CacheUnitEvent";
 236     }
 237
 238
 239     /** Constructs a resource event. */
 240     CacheUnitEvent();
 241     virtual ~CacheUnitEvent() {}
 242
 243     /** Processes a resource event. */
 244     virtual void process();
 245 };
 246
 247 class CacheRequest : public ResourceRequest
 248 {
 249   public:
 250     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 251                  int slot_num, unsigned cmd, int req_size,
 252                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
 253         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 254           pktCmd(pkt_cmd), memReq(NULL), reqData(NULL), dataPkt(NULL),
 255           retryPkt(NULL), memAccComplete(false), memAccPending(false),
 256           tlbStall(false)
 257     { }
 258
 259
 260     virtual ~CacheRequest()
 261     {
 262         if (reqData) {
 263             delete [] reqData;
 264         }
 265     }
 266
 267     virtual PacketDataPtr getData()
 268     {   return reqData; }
 269
 270     void
 271     setMemAccCompleted(bool completed = true)
 272     {
 273         memAccComplete = completed;
 274     }
 275
 276     bool isMemAccComplete() { return memAccComplete; }
 277
 278     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 279     bool isMemAccPending() { return memAccPending; }
 280
 281     //Make this data private/protected!
 282     MemCmd::Command pktCmd;
 283     RequestPtr memReq;
 284     PacketDataPtr reqData;
 285     PacketPtr dataPkt;
 286     PacketPtr retryPkt;
 287
 288     bool memAccComplete;
 289     bool memAccPending;
 290     bool tlbStall;
 291 };
 292
 293 class CacheReqPacket : public Packet
 294 {
 295   public:
 296     CacheReqPacket(CacheRequest *_req,
 297                    Command _cmd, short _dest)
 298         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
 299     {
 300
 301     }
 302
 303     CacheRequest *cacheReq;
 304 };
 305
 306 #endif //__CPU_CACHE_UNIT_HH__