2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
33 #define __CPU_INORDER_CACHE_UNIT_HH__
39 #include "arch/predecoder.hh"
40 #include "arch/tlb.hh"
41 #include "base/hashmap.hh"
42 #include "config/the_isa.hh"
43 #include "cpu/inorder/inorder_dyn_inst.hh"
44 #include "cpu/inorder/pipeline_traits.hh"
45 #include "cpu/inorder/resource.hh"
46 #include "mem/packet.hh"
47 #include "mem/packet_access.hh"
48 #include "mem/port.hh"
49 #include "params/InOrderCPU.hh"
50 #include "sim/sim_object.hh"
53 typedef CacheRequest* CacheReqPtr;
56 typedef CacheReqPacket* CacheReqPktPtr;
58 class CacheUnit : public Resource
61 typedef ThePipeline::DynInstPtr DynInstPtr;
64 CacheUnit(std::string res_name, int res_id, int res_width,
65 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
74 CompleteSecondSplitRead,
75 CompleteSecondSplitWrite
79 /** CachePort class for the Cache Unit. Handles doing the
80 * communication with the cache/memory.
82 class CachePort : public Port
85 /** Pointer to cache port unit */
86 CacheUnit *cachePortUnit;
89 /** Default constructor. */
90 CachePort(CacheUnit *_cachePortUnit)
91 : Port(_cachePortUnit->name() + "-cache-port",
92 (MemObject*)_cachePortUnit->cpu),
93 cachePortUnit(_cachePortUnit), snoopRangeSent(false)
98 void setPeer(Port *port);
101 /** Atomic version of receive. Panics. */
102 Tick recvAtomic(PacketPtr pkt);
104 /** Functional version of receive.*/
105 void recvFunctional(PacketPtr pkt);
107 /** Receives status change. Other than range changing, panics. */
108 void recvStatusChange(Status status);
110 /** Returns the address ranges of this device. */
111 void getDeviceAddressRanges(AddrRangeList &resp,
113 { resp.clear(); snoop = true; }
115 /** Timing version of receive */
116 bool recvTiming(PacketPtr pkt);
118 /** Handles doing a retry of a failed fetch. */
124 ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
125 int res_idx, int slot_num,
128 ResReqPtr findRequest(DynInstPtr inst);
129 ResReqPtr findRequest(DynInstPtr inst, int idx);
131 void requestAgain(DynInstPtr inst, bool &try_request);
133 virtual int getSlot(DynInstPtr inst);
135 /** Executes one of the commands from the "Command" enum */
136 virtual void execute(int slot_num);
138 virtual void squash(DynInstPtr inst, int stage_num,
139 InstSeqNum squash_seq_num, ThreadID tid);
141 void squashDueToMemStall(DynInstPtr inst, int stage_num,
142 InstSeqNum squash_seq_num, ThreadID tid);
144 virtual void squashCacheRequest(CacheReqPtr req_ptr);
146 /** After memory request is completedd in the cache, then do final
147 processing to complete the request in the CPU.
149 virtual void processCacheCompletion(PacketPtr pkt);
151 /** Create request that will interface w/TLB and Memory objects */
152 virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
153 int acc_size, int flags);
155 void finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req);
157 void buildDataPacket(CacheRequest *cache_req);
159 bool processSquash(CacheReqPacket *cache_pkt);
161 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
165 /** Returns a specific port. */
166 Port *getPort(const std::string &if_name, int idx);
168 Fault read(DynInstPtr inst, Addr addr,
169 uint8_t *data, unsigned size, unsigned flags);
171 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
172 Addr addr, unsigned flags, uint64_t *res);
174 void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
175 int flags, TheISA::TLB::Mode tlb_mode);
177 /** Read/Write on behalf of an instruction.
178 * curResSlot needs to be a valid value in instruction.
180 void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
181 CacheReqPtr split_req=NULL);
183 uint64_t getMemData(Packet *packet);
185 void setAddrDependency(DynInstPtr inst);
186 virtual void removeAddrDependency(DynInstPtr inst);
189 /** Cache interface. */
190 CachePort *cachePort;
192 bool cachePortBlocked;
194 std::list<Addr> addrList[ThePipeline::MaxThreads];
196 m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
203 /** Align a PC to the start of the Cache block. */
204 Addr cacheBlockAlign(Addr addr)
206 return (addr & ~(cacheBlkMask));
209 bool tlbBlocked[ThePipeline::MaxThreads];
210 InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads];
216 class CacheUnitEvent : public ResourceEvent {
218 const std::string name() const
220 return "CacheUnitEvent";
224 /** Constructs a resource event. */
226 virtual ~CacheUnitEvent() {}
228 /** Processes a resource event. */
232 //@todo: Move into CacheUnit Class for private access to "valid" field
233 class CacheRequest : public ResourceRequest
236 CacheRequest(CacheUnit *cres)
237 : ResourceRequest(cres), memReq(NULL), reqData(NULL),
238 dataPkt(NULL), memAccComplete(false),
239 memAccPending(false), tlbStall(false), splitAccess(false),
240 splitAccessNum(-1), split2ndAccess(false),
241 fetchBufferFill(false)
244 virtual ~CacheRequest()
246 if (reqData && !splitAccess)
250 void setRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num,
251 unsigned _cmd, MemCmd::Command pkt_cmd, int idx)
256 ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num, _cmd);
261 virtual PacketDataPtr getData()
265 setMemAccCompleted(bool completed = true)
267 memAccComplete = completed;
272 return split2ndAccess;
275 bool isMemAccComplete() { return memAccComplete; }
277 void setMemAccPending(bool pending = true) { memAccPending = pending; }
278 bool isMemAccPending() { return memAccPending; }
280 //Make this data private/protected!
281 MemCmd::Command pktCmd;
283 PacketDataPtr reqData;
284 CacheReqPacket *dataPkt;
295 /** Should we expect block from cache access or fetch buffer? */
296 bool fetchBufferFill;
299 class CacheReqPacket : public Packet
302 CacheReqPacket(CacheRequest *_req,
303 Command _cmd, short _dest, int _idx = 0)
304 : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
305 instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
310 CacheRequest *cacheReq;
313 PacketDataPtr reqData;
317 #endif //__CPU_CACHE_UNIT_HH__