src/cpu/inorder/resources/cache_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
  33 #define __CPU_INORDER_CACHE_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource.hh"
  45 #include "mem/packet.hh"
  46 #include "mem/packet_access.hh"
  47 #include "mem/port.hh"
  48 #include "params/InOrderCPU.hh"
  49 #include "sim/sim_object.hh"
  50
  51 class CacheRequest;
  52 typedef CacheRequest* CacheReqPtr;
  53
  54 class CacheReqPacket;
  55 typedef CacheReqPacket* CacheReqPktPtr;
  56
  57 class CacheUnit : public Resource
  58 {
  59   public:
  60     typedef ThePipeline::DynInstPtr DynInstPtr;
  61
  62   public:
  63     CacheUnit(std::string res_name, int res_id, int res_width,
  64               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  65
  66     enum Command {
  67         InitiateFetch,
  68         CompleteFetch,
  69         InitiateReadData,
  70         CompleteReadData,
  71         InitiateWriteData,
  72         CompleteWriteData,
  73         Fetch,
  74         ReadData,
  75         WriteData
  76     };
  77
  78   public:
  79     /** CachePort class for the Cache Unit.  Handles doing the
  80      * communication with the cache/memory.
  81      */
  82     class CachePort : public Port
  83     {
  84       protected:
  85         /** Pointer to cache port unit */
  86         CacheUnit *cachePortUnit;
  87
  88       public:
  89         /** Default constructor. */
  90         CachePort(CacheUnit *_cachePortUnit)
  91           : Port(_cachePortUnit->name() + "-cache-port",
  92                  (MemObject*)_cachePortUnit->cpu),
  93             cachePortUnit(_cachePortUnit)
  94         { }
  95
  96         bool snoopRangeSent;
  97
  98       protected:
  99         /** Atomic version of receive.  Panics. */
 100         virtual Tick recvAtomic(PacketPtr pkt);
 101
 102         /** Functional version of receive.  Panics. */
 103         virtual void recvFunctional(PacketPtr pkt);
 104
 105         /** Receives status change.  Other than range changing, panics. */
 106         virtual void recvStatusChange(Status status);
 107
 108         /** Returns the address ranges of this device. */
 109         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 110                                             AddrRangeList &snoop)
 111         { resp.clear(); snoop.clear(); }
 112
 113         /** Timing version of receive. Handles setting fetch to the
 114          * proper status to start fetching. */
 115         virtual bool recvTiming(PacketPtr pkt);
 116
 117         /** Handles doing a retry of a failed fetch. */
 118         virtual void recvRetry();
 119     };
 120
 121     void init();
 122
 123     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 124                                         int res_idx, int slot_num,
 125                                         unsigned cmd);
 126
 127     void requestAgain(DynInstPtr inst, bool &try_request);
 128
 129     int getSlot(DynInstPtr inst);
 130
 131     void freeSlot(int slot_num);
 132
 133     /** Execute the function of this resource. The Default is action
 134      *  is to do nothing. More specific models will derive from this
 135      *  class and define their own execute function.
 136      */
 137     void execute(int slot_num);
 138
 139     void squash(DynInstPtr inst, int stage_num,
 140                 InstSeqNum squash_seq_num, ThreadID tid);
 141
 142     void squashDueToMemStall(DynInstPtr inst, int stage_num,
 143                              InstSeqNum squash_seq_num, ThreadID tid);
 144
 145     /** Processes cache completion event. */
 146     void processCacheCompletion(PacketPtr pkt);
 147
 148     void recvRetry();
 149
 150     /** Align a PC to the start of an I-cache block. */
 151     Addr cacheBlockAlignPC(Addr addr)
 152     {
 153         return (addr & ~(cacheBlkMask));
 154     }
 155
 156     /** Returns a specific port. */
 157     Port *getPort(const std::string &if_name, int idx);
 158
 159     template <class T>
 160     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 161
 162     template <class T>
 163     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 164                         uint64_t *res);
 165
 166     Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 167                       int flags,  TheISA::TLB::Mode tlb_mode);
 168
 169     /** Read/Write on behalf of an instruction.
 170      *  curResSlot needs to be a valid value in instruction.
 171      */
 172     Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL);
 173
 174     void prefetch(DynInstPtr inst);
 175
 176     void writeHint(DynInstPtr inst);
 177
 178     uint64_t getMemData(Packet *packet);
 179
 180   protected:
 181     /** Cache interface. */
 182     CachePort *cachePort;
 183
 184     bool cachePortBlocked;
 185
 186     std::vector<Addr> addrList[ThePipeline::MaxThreads];
 187
 188     std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 189
 190   public:
 191     int cacheBlkSize;
 192
 193     int cacheBlkMask;
 194
 195     /** Align a PC to the start of the Cache block. */
 196     Addr cacheBlockAlign(Addr addr)
 197     {
 198         return (addr & ~(cacheBlkMask));
 199     }
 200
 201     /** The mem line being fetched. */
 202     uint8_t *fetchData[ThePipeline::MaxThreads];
 203
 204     /** @TODO: Move functionaly of fetching more than
 205         one instruction to 'fetch unit'*/
 206     /** The Addr of the cacheline that has been loaded. */
 207     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 208     //unsigned fetchOffset[ThePipeline::MaxThreads];
 209
 210     TheISA::Predecoder predecoder;
 211
 212     bool tlbBlocked[ThePipeline::MaxThreads];
 213
 214     TheISA::TLB* tlb();
 215
 216     TheISA::TLB *_tlb;
 217 };
 218
 219 class CacheUnitEvent : public ResourceEvent {
 220   public:
 221     const std::string name() const
 222     {
 223         return "CacheUnitEvent";
 224     }
 225
 226
 227     /** Constructs a resource event. */
 228     CacheUnitEvent();
 229     virtual ~CacheUnitEvent() {}
 230
 231     /** Processes a resource event. */
 232     virtual void process();
 233 };
 234
 235 class CacheRequest : public ResourceRequest
 236 {
 237   public:
 238     CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
 239                  int slot_num, unsigned cmd, int req_size,
 240                  MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
 241         : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
 242           pktCmd(pkt_cmd), memReq(NULL), reqData(NULL), dataPkt(NULL),
 243           retryPkt(NULL), memAccComplete(false), memAccPending(false),
 244           tlbStall(false)
 245     { }
 246
 247
 248     virtual ~CacheRequest()
 249     {
 250         if (reqData) {
 251             delete [] reqData;
 252         }
 253     }
 254
 255     virtual PacketDataPtr getData()
 256     {   return reqData; }
 257
 258     void
 259     setMemAccCompleted(bool completed = true)
 260     {
 261         memAccComplete = completed;
 262     }
 263
 264     bool isMemAccComplete() { return memAccComplete; }
 265
 266     void setMemAccPending(bool pending = true) { memAccPending = pending; }
 267     bool isMemAccPending() { return memAccPending; }
 268
 269     //Make this data private/protected!
 270     MemCmd::Command pktCmd;
 271     RequestPtr memReq;
 272     PacketDataPtr reqData;
 273     PacketPtr dataPkt;
 274     PacketPtr retryPkt;
 275
 276     bool memAccComplete;
 277     bool memAccPending;
 278     bool tlbStall;
 279 };
 280
 281 class CacheReqPacket : public Packet
 282 {
 283   public:
 284     CacheReqPacket(CacheRequest *_req,
 285                    Command _cmd, short _dest)
 286         : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
 287     {
 288
 289     }
 290
 291     CacheRequest *cacheReq;
 292 };
 293
 294 #endif //__CPU_CACHE_UNIT_HH__