2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CACHE_UNIT_HH__
33 #define __CPU_INORDER_CACHE_UNIT_HH__
39 #include "arch/predecoder.hh"
40 #include "cpu/inorder/resource.hh"
41 #include "cpu/inorder/inorder_dyn_inst.hh"
42 #include "mem/packet.hh"
43 #include "mem/packet_access.hh"
44 #include "mem/port.hh"
45 #include "cpu/inorder/pipeline_traits.hh"
46 #include "sim/sim_object.hh"
48 #include "params/InOrderCPU.hh"
51 typedef CacheRequest* CacheReqPtr;
54 typedef CacheReqPacket* CacheReqPktPtr;
56 class CacheUnit : public Resource
59 typedef ThePipeline::DynInstPtr DynInstPtr;
62 CacheUnit(std::string res_name, int res_id, int res_width,
63 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
64 virtual ~CacheUnit() {}
79 /** CachePort class for the Cache Unit. Handles doing the
80 * communication with the cache/memory.
82 class CachePort : public Port
85 /** Pointer to cache port unit */
86 CacheUnit *cachePortUnit;
89 /** Default constructor. */
90 CachePort(CacheUnit *_cachePortUnit)
91 : Port(_cachePortUnit->name() + "-cache-port",
92 (MemObject*)_cachePortUnit->cpu),
93 cachePortUnit(_cachePortUnit)
99 /** Atomic version of receive. Panics. */
100 virtual Tick recvAtomic(PacketPtr pkt);
102 /** Functional version of receive. Panics. */
103 virtual void recvFunctional(PacketPtr pkt);
105 /** Receives status change. Other than range changing, panics. */
106 virtual void recvStatusChange(Status status);
108 /** Returns the address ranges of this device. */
109 virtual void getDeviceAddressRanges(AddrRangeList &resp,
110 AddrRangeList &snoop)
111 { resp.clear(); snoop.clear(); }
113 /** Timing version of receive. Handles setting fetch to the
114 * proper status to start fetching. */
115 virtual bool recvTiming(PacketPtr pkt);
117 /** Handles doing a retry of a failed fetch. */
118 virtual void recvRetry();
121 enum CachePortStatus {
127 ///virtual void init();
129 virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
130 int res_idx, int slot_num,
133 void requestAgain(DynInstPtr inst, bool &try_request);
135 int getSlot(DynInstPtr inst);
137 void freeSlot(int slot_num);
139 /** Execute the function of this resource. The Default is action
140 * is to do nothing. More specific models will derive from this
141 * class and define their own execute function.
143 void execute(int slot_num);
145 void squash(DynInstPtr inst, int stage_num,
146 InstSeqNum squash_seq_num, unsigned tid);
148 /** Processes cache completion event. */
149 void processCacheCompletion(PacketPtr pkt);
153 /** Align a PC to the start of an I-cache block. */
154 Addr cacheBlockAlignPC(Addr addr)
156 return (addr & ~(cacheBlkMask));
159 /** Returns a specific port. */
160 Port *getPort(const std::string &if_name, int idx);
162 /** Read/Write on behalf of an instruction.
163 * curResSlot needs to be a valid value in instruction.
165 Fault doDataAccess(DynInstPtr inst, uint64_t *write_result=NULL);
167 void prefetch(DynInstPtr inst);
169 void writeHint(DynInstPtr inst);
171 uint64_t getMemData(Packet *packet);
174 /** Cache interface. */
175 CachePort *cachePort;
177 CachePortStatus cacheStatus;
179 CacheReqPtr retryReq;
187 std::vector<Addr> addrList;
189 std::map<Addr, InstSeqNum> addrMap;
196 /** Align a PC to the start of the Cache block. */
197 Addr cacheBlockAlign(Addr addr)
199 return (addr & ~(cacheBlkMask));
202 /** The mem line being fetched. */
203 uint8_t *fetchData[ThePipeline::MaxThreads];
205 /** @TODO: Move functionaly of fetching more than
206 one instruction to 'fetch unit'*/
207 /** The Addr of the cacheline that has been loaded. */
208 //Addr cacheBlockAddr[ThePipeline::MaxThreads];
209 //unsigned fetchOffset[ThePipeline::MaxThreads];
211 TheISA::Predecoder predecoder;
214 struct CacheSchedEntry : public ThePipeline::ScheduleEntry
221 CacheSchedEntry(int stage_num, int _priority, int res_num,
222 MemCmd::Command pkt_cmd, EntryType _type = FetchAccess)
223 : ScheduleEntry(stage_num, _priority, res_num), pktCmd(pkt_cmd),
227 MemCmd::Command pktCmd;
231 class CacheRequest : public ResourceRequest
234 CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
235 int slot_num, unsigned cmd, int req_size,
236 MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
237 : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
238 pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
240 if (cmd == CacheUnit::InitiateFetch ||
241 cmd == CacheUnit::CompleteFetch ||
242 cmd == CacheUnit::Fetch) {
243 memReq = inst->fetchMemReq;
245 memReq = inst->dataMemReq;
248 //@ Only matters for Fetch / Read requests
249 // Don't allocate for Writes!
250 reqData = new uint8_t[req_size];
254 virtual ~CacheRequest()
259 // Can get rid of packet and packet request now
267 // Can get rid of packet and packet request now
270 delete retryPkt->req;
277 virtual PacketDataPtr getData()
281 setMemAccCompleted(bool completed = true)
283 memAccComplete = completed;
286 bool isMemAccComplete() { return memAccComplete; }
288 void setMemAccPending(bool pending = true) { memAccPending = pending; }
289 bool isMemAccPending() { return memAccPending; }
291 //Make this data private/protected!
292 MemCmd::Command pktCmd;
294 PacketDataPtr reqData;
302 class CacheReqPacket : public Packet
305 CacheReqPacket(CacheRequest *_req,
306 Command _cmd, short _dest)
307 : Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
312 CacheRequest *cacheReq;
315 #endif //__CPU_CACHE_UNIT_HH__