src/cpu/inorder/resources/decode_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/decode_unit.hh"
  34
  35 using namespace TheISA;
  36 using namespace ThePipeline;
  37 using namespace std;
  38
  39 DecodeUnit::DecodeUnit(std::string res_name, int res_id, int res_width,
  40                        int res_latency, InOrderCPU *_cpu,
  41                        ThePipeline::Params *params)
  42     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  43 {
  44     for (ThreadID tid = 0; tid < MaxThreads; tid++) {
  45         regDepMap[tid] = &cpu->archRegDepMap[tid];
  46     }
  47 }
  48
  49 void
  50 DecodeUnit::execute(int slot_num)
  51 {
  52     ResourceRequest* decode_req = reqMap[slot_num];
  53     DynInstPtr inst = reqMap[slot_num]->inst;
  54     ThreadID tid = inst->readTid();
  55
  56     switch (decode_req->cmd)
  57     {
  58       case DecodeInst:
  59         {
  60             inst->setBackSked(cpu->createBackEndSked(inst));
  61
  62             if (inst->backSked != NULL) {
  63                 DPRINTF(InOrderDecode,
  64                     "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
  65                     tid, inst->seqNum);
  66                 regDepMap[tid]->insert(inst);
  67
  68                 //inst->printSked();
  69
  70                 decode_req->done();
  71             } else {
  72                 DPRINTF(Resource,
  73                     "[tid:%i] Static Inst not available to decode.\n", tid);
  74                 DPRINTF(Resource,
  75                     "Unable to create schedule for instruction [sn:%i] \n",
  76                     inst->seqNum);
  77                 DPRINTF(InOrderStall, "STALL: \n");
  78                 decode_req->done(false);
  79             }
  80         }
  81         break;
  82
  83       default:
  84         fatal("Unrecognized command to %s", resName);
  85     }
  86 }
  87
  88
  89 void
  90 DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
  91                    ThreadID tid)
  92 {
  93     DPRINTF(InOrderDecode,
  94             "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
  95             tid, stage_num, squash_seq_num);
  96
  97     //cpu->removeInstsUntil(squash_seq_num, tid);
  98 }