Yet another merge with the main repository.
[gem5.git] / src / cpu / inorder / resources / decode_unit.cc
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #include "config/the_isa.hh"
33 #include "cpu/inorder/resources/decode_unit.hh"
34 #include "debug/InOrderDecode.hh"
35 #include "debug/InOrderStall.hh"
36 #include "debug/Resource.hh"
37
38 using namespace TheISA;
39 using namespace ThePipeline;
40 using namespace std;
41
42 DecodeUnit::DecodeUnit(std::string res_name, int res_id, int res_width,
43 int res_latency, InOrderCPU *_cpu,
44 ThePipeline::Params *params)
45 : Resource(res_name, res_id, res_width, res_latency, _cpu)
46 {
47 for (ThreadID tid = 0; tid < MaxThreads; tid++) {
48 regDepMap[tid] = &cpu->archRegDepMap[tid];
49 }
50 }
51
52 void
53 DecodeUnit::execute(int slot_num)
54 {
55 ResourceRequest* decode_req = reqs[slot_num];
56 DynInstPtr inst = reqs[slot_num]->inst;
57
58 switch (decode_req->cmd)
59 {
60 case DecodeInst:
61 {
62
63 if (inst->fault != NoFault) {
64 inst->setBackSked(cpu->faultSked);
65 DPRINTF(InOrderDecode,"[tid:%i]: Fault found for instruction [sn:%i]\n",
66 inst->readTid(), inst->seqNum);
67 } else {
68 assert(!inst->staticInst->isMacroop());
69 inst->setBackSked(cpu->createBackEndSked(inst));
70 DPRINTF(InOrderDecode,"Decoded instruction [sn:%i]: %s : 0x%x\n",
71 inst->seqNum, inst->instName(),
72 inst->staticInst->machInst);
73 }
74
75 if (inst->backSked != NULL) {
76 DPRINTF(InOrderDecode,
77 "[tid:%i]: Back End Schedule created for %s [sn:%i].\n",
78 inst->readTid(), inst->instName(), inst->seqNum);
79 decode_req->done();
80 } else {
81 DPRINTF(Resource,
82 "[tid:%i] Static Inst not available to decode.\n",
83 inst->readTid());
84 DPRINTF(Resource,
85 "Unable to create schedule for instruction [sn:%i] \n",
86 inst->seqNum);
87 DPRINTF(InOrderStall, "STALL: \n");
88 decode_req->done(false);
89 }
90 }
91 break;
92
93 default:
94 fatal("Unrecognized command to %s", resName);
95 }
96 }
97