src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "cpu/inorder/resources/execution_unit.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/resource_pool.hh"
  38 #include "debug/Fault.hh"
  39 #include "debug/InOrderExecute.hh"
  40 #include "debug/InOrderStall.hh"
  41 #include "sim/full_system.hh"
  42
  43 using namespace std;
  44 using namespace ThePipeline;
  45
  46 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  47                              Cycles res_latency, InOrderCPU *_cpu,
  48                              ThePipeline::Params *params)
  49     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  50       lastExecuteTick(0), lastControlTick(0)
  51 { }
  52
  53 void
  54 ExecutionUnit::regStats()
  55 {
  56     predictedTakenIncorrect
  57         .name(name() + ".predictedTakenIncorrect")
  58         .desc("Number of Branches Incorrectly Predicted As Taken.");
  59
  60     predictedNotTakenIncorrect
  61         .name(name() + ".predictedNotTakenIncorrect")
  62         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  63
  64     executions
  65         .name(name() + ".executions")
  66         .desc("Number of Instructions Executed.");
  67
  68
  69     predictedIncorrect
  70         .name(name() + ".mispredicted")
  71         .desc("Number of Branches Incorrectly Predicted");
  72
  73     predictedCorrect
  74         .name(name() + ".predicted")
  75         .desc("Number of Branches Incorrectly Predicted");
  76
  77     mispredictPct
  78         .name(name() + ".mispredictPct")
  79         .desc("Percentage of Incorrect Branches Predicts")
  80         .precision(6);
  81     mispredictPct = (predictedIncorrect /
  82                      (predictedCorrect + predictedIncorrect)) * 100;
  83
  84     Resource::regStats();
  85 }
  86
  87 void
  88 ExecutionUnit::execute(int slot_num)
  89 {
  90     ResourceRequest* exec_req = reqs[slot_num];
  91     DynInstPtr inst = reqs[slot_num]->inst;
  92     if (inst->fault != NoFault) {
  93         DPRINTF(InOrderExecute,
  94                 "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
  95                 "next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(),
  96                 inst->pcState());
  97         exec_req->done();
  98         return;
  99     }
 100
 101     Fault fault = NoFault;
 102     Tick cur_tick = curTick();
 103     unsigned stage_num = exec_req->getStageNum();
 104     ThreadID tid = inst->readTid();
 105 #if TRACING_ON
 106     InstSeqNum seq_num = inst->seqNum;
 107 #endif
 108
 109     switch (exec_req->cmd)
 110     {
 111       case ExecuteInst:
 112         {
 113             if (inst->isNop()) {
 114                 DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
 115                         "of %s.\n", inst->readTid(), seq_num, inst->pcState(),
 116                         inst->instName());
 117                 inst->setExecuted();
 118                 exec_req->done();
 119                 return;
 120             } else {
 121                 DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 122                         inst->readTid(), seq_num, inst->pcState(), inst->instName());
 123             }
 124
 125             if (cur_tick != lastExecuteTick) {
 126                 lastExecuteTick = cur_tick;
 127             }
 128
 129             //@todo: handle address generation here
 130             assert(!inst->isMemRef());
 131
 132             if (inst->isControl()) {
 133                 if (lastControlTick == cur_tick) {
 134                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 135                             "Inst Per Cycle. Blocking Request.\n");
 136                     exec_req->done(false);
 137                     return;
 138                 }
 139                 lastControlTick = curTick();
 140
 141                 // Evaluate Branch
 142                 fault = inst->execute();
 143
 144                 // Should unconditional control , pc relative count as an
 145                 // execution??? Probably not.
 146                 executions++;
 147
 148                 if (fault == NoFault) {
 149                     inst->setExecuted();
 150
 151                     if (inst->mispredicted()) {
 152                         assert(inst->isControl());
 153
 154                         // Set up Squash Generated By this Misprediction
 155                         TheISA::PCState pc = inst->pcState();
 156                         TheISA::advancePC(pc, inst->staticInst);
 157                         inst->setPredTarg(pc);
 158                         inst->setSquashInfo(stage_num);
 159                         setupSquash(inst, stage_num, tid);
 160
 161                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i] Squashing from "
 162                                 "stage %i. Redirecting  fetch to %s.\n", tid,
 163                                 inst->seqNum, stage_num, pc);
 164                         DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 165                                 " misprediction at %s\n", tid, inst->pcState());
 166
 167                         if (inst->predTaken()) {
 168                             predictedTakenIncorrect++;
 169                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 170                                     "PC %s ... Mispredicts! "
 171                                     "(Prediction: Taken)\n",
 172                                     tid, inst->seqNum,
 173                                     inst->staticInst->disassemble(
 174                                         inst->instAddr()),
 175                                     inst->pcState());
 176                         } else {
 177                             predictedNotTakenIncorrect++;
 178                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 179                                     "PC %s ... Mispredicts! "
 180                                     "(Prediction: Not Taken)\n",
 181                                     tid, inst->seqNum,
 182                                     inst->staticInst->disassemble(
 183                                         inst->instAddr()),
 184                                     inst->pcState());
 185                         }
 186                         predictedIncorrect++;
 187                     } else {
 188                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 189                                 "Correct.\n", inst->readTid(), seq_num);
 190                         predictedCorrect++;
 191                     }
 192
 193                     exec_req->done();
 194                 } else {
 195                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 196                             inst->readTid(), inst->seqNum, fault->name());
 197                     inst->fault = fault;
 198                     exec_req->done();
 199                 }
 200             } else {
 201                 // Regular ALU instruction
 202                 fault = inst->execute();
 203                 executions++;
 204
 205                 if (fault == NoFault) {
 206                     inst->setExecuted();
 207
 208 #if TRACING_ON
 209                     for (int didx = 0; didx < inst->numDestRegs(); didx++)
 210                         if (inst->resultType(didx) == InOrderDynInst::Float ||
 211                             inst->resultType(didx) == InOrderDynInst::FloatBits ||
 212                             inst->resultType(didx) == InOrderDynInst::Double)
 213                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 214                                     "of FP execution is %08f (%x).\n", inst->readTid(),
 215                                     seq_num, didx, inst->readFloatResult(didx),
 216                                     inst->readFloatBitsResult(didx));
 217                         else
 218                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 219                                     "of Int execution is 0x%x.\n", inst->readTid(),
 220                                     seq_num, didx, inst->readIntResult(didx));
 221 #endif
 222
 223                     if (!FullSystem) {
 224                         // The Syscall might change the PC, so conservatively
 225                         // squash everything behing it
 226                         if (inst->isSyscall()) {
 227                             inst->setSquashInfo(stage_num);
 228                             setupSquash(inst, stage_num, tid);
 229                         }
 230                     }
 231                 } else {
 232                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 233                             "fault.\n", inst->readTid(), seq_num, fault->name());
 234                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 235                             inst->readTid(), inst->seqNum, fault->name());
 236                     inst->fault = fault;
 237                 }
 238
 239                 exec_req->done();
 240             }
 241         }
 242         break;
 243
 244       default:
 245         fatal("Unrecognized command to %s", resName);
 246     }
 247 }
 248
 249