src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  43     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  44 { }
  45
  46 void
  47 ExecutionUnit::regStats()
  48 {
  49     predictedTakenIncorrect
  50         .name(name() + ".predictedTakenIncorrect")
  51         .desc("Number of Branches Incorrectly Predicted As Taken.");
  52
  53     predictedNotTakenIncorrect
  54         .name(name() + ".predictedNotTakenIncorrect")
  55         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  56
  57     Resource::regStats();
  58 }
  59
  60 void
  61 ExecutionUnit::execute(int slot_num)
  62 {
  63     ResourceRequest* exec_req = reqMap[slot_num];
  64     DynInstPtr inst = reqMap[slot_num]->inst;
  65     Fault fault = reqMap[slot_num]->fault;
  66     ThreadID tid = inst->readTid();
  67     int seq_num = inst->seqNum;
  68
  69     exec_req->fault = NoFault;
  70
  71     DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
  72             tid, seq_num, inst->readPC(), inst->instName());
  73
  74     switch (exec_req->cmd)
  75     {
  76       case ExecuteInst:
  77         {
  78             if (inst->isMemRef()) {
  79                 panic("%s not configured to handle memory ops.\n", resName);
  80             } else if (inst->isControl()) {
  81                 // Evaluate Branch
  82                 fault = inst->execute();
  83
  84                 inst->setExecuted();
  85
  86                 if (fault == NoFault) {
  87                     // If branch is mispredicted, then signal squash
  88                     // throughout all stages behind the pipeline stage
  89                     // that got squashed.
  90                     if (inst->mispredicted()) {
  91                         int stage_num = exec_req->getStageNum();
  92                         ThreadID tid = inst->readTid();
  93
  94                         // If it's a branch ...
  95                         if (inst->isDirectCtrl()) {
  96                             assert(!inst->isIndirectCtrl());
  97
  98                             if (inst->predTaken() && inst->isCondDelaySlot()) {
  99                                 inst->bdelaySeqNum = seq_num;
 100                                 inst->setPredTarg(inst->nextPC);
 101
 102                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst"
 103                                         "[sn:%i] PC %#x mispredicted as taken.\n", tid,
 104                                         seq_num, inst->PC);
 105                             } else if (!inst->predTaken() && inst->isCondDelaySlot()) {
 106                                 inst->bdelaySeqNum = seq_num;
 107                                 inst->setPredTarg(inst->nextPC);
 108                                 inst->procDelaySlotOnMispred = true;
 109
 110                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst."
 111                                         "[sn:%i] PC %#x mispredicted as not taken.\n", tid,
 112                                         seq_num, inst->PC);
 113                             } else {
 114 #if ISA_HAS_DELAY_SLOT
 115                                 inst->bdelaySeqNum = seq_num + 1;
 116                                 inst->setPredTarg(inst->nextNPC);
 117 #else
 118                                 inst->bdelaySeqNum = seq_num;
 119                                 inst->setPredTarg(inst->nextPC);
 120 #endif
 121                                 DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at "
 122                                         "[sn:%i] PC %#x,\n\t squashing after delay slot "
 123                                         "instruction [sn:%i].\n",
 124                                         tid, seq_num, inst->PC, inst->bdelaySeqNum);
 125                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch "
 126                                         "misprediction at %#x\n", tid, inst->PC);
 127                             }
 128
 129                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
 130                                     inst->readPredTarg());
 131
 132                         } else if(inst->isIndirectCtrl()){
 133 #if ISA_HAS_DELAY_SLOT
 134                             inst->setPredTarg(inst->nextNPC);
 135                             inst->bdelaySeqNum = seq_num + 1;
 136 #else
 137                             inst->setPredTarg(inst->nextPC);
 138                             inst->bdelaySeqNum = seq_num;
 139 #endif
 140
 141                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
 142                                     inst->readPredTarg());
 143                         } else {
 144                             panic("Non-control instruction (%s) mispredicting?!!",
 145                                   inst->staticInst->getName());
 146                         }
 147
 148                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will start from stage %i.\n",
 149                                 tid, stage_num);
 150
 151                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 152
 153                         inst->squashingStage = stage_num;
 154
 155                         // Squash throughout other resources
 156                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 157                                                     inst, 0, 0, tid);
 158
 159                         if (inst->predTaken()) {
 160                             predictedTakenIncorrect++;
 161                         } else {
 162                             predictedNotTakenIncorrect++;
 163                         }
 164                     } else {
 165                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
 166                                 inst->readTid(), seq_num);
 167                     }
 168
 169                     exec_req->done();
 170                 } else {
 171                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 172                 }
 173             } else {
 174                 // Regular ALU instruction
 175                 fault = inst->execute();
 176
 177                 if (fault == NoFault) {
 178                     inst->setExecuted();
 179
 180                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
 181                             inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
 182                             inst->readFloatResult(0) : inst->readIntResult(0));
 183
 184                     exec_req->done();
 185                 } else {
 186                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 187                     cpu->trap(fault, tid);
 188                 }
 189             }
 190         }
 191         break;
 192
 193       default:
 194         fatal("Unrecognized command to %s", resName);
 195     }
 196 }
 197
 198