src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "cpu/inorder/resources/execution_unit.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/resource_pool.hh"
  38 #include "debug/InOrderExecute.hh"
  39 #include "debug/InOrderStall.hh"
  40
  41 using namespace std;
  42 using namespace ThePipeline;
  43
  44 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  45                              int res_latency, InOrderCPU *_cpu,
  46                              ThePipeline::Params *params)
  47     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  48       lastExecuteTick(0), lastControlTick(0), serializeTick(0)
  49 { }
  50
  51 void
  52 ExecutionUnit::regStats()
  53 {
  54     predictedTakenIncorrect
  55         .name(name() + ".predictedTakenIncorrect")
  56         .desc("Number of Branches Incorrectly Predicted As Taken.");
  57
  58     predictedNotTakenIncorrect
  59         .name(name() + ".predictedNotTakenIncorrect")
  60         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  61
  62     executions
  63         .name(name() + ".executions")
  64         .desc("Number of Instructions Executed.");
  65
  66
  67     predictedIncorrect
  68         .name(name() + ".mispredicted")
  69         .desc("Number of Branches Incorrectly Predicted");
  70
  71     predictedCorrect
  72         .name(name() + ".predicted")
  73         .desc("Number of Branches Incorrectly Predicted");
  74
  75     mispredictPct
  76         .name(name() + ".mispredictPct")
  77         .desc("Percentage of Incorrect Branches Predicts")
  78         .precision(6);
  79     mispredictPct = (predictedIncorrect /
  80                      (predictedCorrect + predictedIncorrect)) * 100;
  81
  82     Resource::regStats();
  83 }
  84
  85 void
  86 ExecutionUnit::execute(int slot_num)
  87 {
  88     ResourceRequest* exec_req = reqs[slot_num];
  89     DynInstPtr inst = reqs[slot_num]->inst;
  90     Fault fault = NoFault;
  91     InstSeqNum seq_num = inst->seqNum;
  92     Tick cur_tick = curTick();
  93
  94     if (cur_tick == serializeTick) {
  95         DPRINTF(InOrderExecute, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
  96                 "All instructions are being serialized this cycle\n",
  97                 inst->readTid(), seq_num, inst->pcState(), inst->instName());
  98         exec_req->done(false);
  99         return;
 100     }
 101
 102
 103     //@todo: may want to make a separate schedule entry for setting
 104     //       destination register dependencies
 105     //@note: typically want to set the output dependencies right
 106     //       before we do any reading or writing of registers
 107     //       (in RegFile Manager(use_def.cc)) but there are some
 108     //       instructions that dont have src regs, so just in case
 109     //       take care of reg. dep. map stuff here
 110     if (!inst->isRegDepEntry()) {
 111         regDepMap[tid]->insert(inst);
 112     }
 113
 114     switch (exec_req->cmd)
 115     {
 116       case ExecuteInst:
 117         {
 118             if (inst->isNop()) {
 119                 DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
 120                         "of %s.\n", inst->readTid(), seq_num, inst->pcState(),
 121                         inst->instName());
 122                 inst->setExecuted();
 123                 exec_req->done();
 124                 return;
 125             } else {
 126                 DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 127                         inst->readTid(), seq_num, inst->pcState(), inst->instName());
 128             }
 129
 130             if (cur_tick != lastExecuteTick) {
 131                 lastExecuteTick = cur_tick;
 132             }
 133
 134             assert(!inst->isMemRef());
 135
 136             if (inst->isSerializeAfter()) {
 137                 serializeTick = cur_tick;
 138                 DPRINTF(InOrderExecute, "Serializing execution after [tid:%i] "
 139                         "[sn:%i] [PC:%s] %s.\n", inst->readTid(), seq_num,
 140                         inst->pcState(), inst->instName());
 141             }
 142
 143             if (inst->isControl()) {
 144                 if (lastControlTick == cur_tick) {
 145                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 146                             "Inst Per Cycle. Blocking Request.\n");
 147                     exec_req->done(false);
 148                     return;
 149                 }
 150                 lastControlTick = curTick();
 151
 152                 // Evaluate Branch
 153                 fault = inst->execute();
 154                 executions++;
 155                 inst->setExecuted();
 156
 157                 if (fault == NoFault) {
 158                     // If branch is mispredicted, then signal squash
 159                     // throughout all stages behind the pipeline stage
 160                     // that got squashed.
 161                     if (inst->mispredicted()) {
 162                         int stage_num = exec_req->getStageNum();
 163                         ThreadID tid = inst->readTid();
 164                         // If it's a branch ...
 165                         if (inst->isDirectCtrl()) {
 166                             assert(!inst->isIndirectCtrl());
 167
 168                             TheISA::PCState pc = inst->pcState();
 169                             TheISA::advancePC(pc, inst->staticInst);
 170                             inst->setPredTarg(pc);
 171
 172                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 173                                 assert(0 && "Not Handling Conditional Delay Slots (1)");
 174                                 inst->bdelaySeqNum = seq_num;
 175                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 176                                         " branch inst [sn:%i] PC %s mis"
 177                                         "predicted as taken.\n", tid,
 178                                         seq_num, inst->pcState());
 179                             } else if (!inst->predTaken() && inst->isCondDelaySlot()) {
 180                                 assert(0 && "Not Handling Conditional Delay Slots (2)");
 181                                 inst->bdelaySeqNum = seq_num;
 182                                 inst->procDelaySlotOnMispred = true;
 183
 184                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 185                                         " branch inst [sn:%i] PC %s mis"
 186                                         "predicted as not taken.\n", tid,
 187                                         seq_num, inst->pcState());
 188                             } else {
 189                                 inst->bdelaySeqNum = seq_num;
 190
 191                                 DPRINTF(InOrderExecute, "[tid:%i]: "
 192                                         "Misprediction detected at "
 193                                         "[sn:%i] PC %s,\n\t squashing after "
 194                                         "delay slot instruction [sn:%i].\n",
 195                                         tid, seq_num, inst->pcState(),
 196                                         inst->bdelaySeqNum);
 197                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 198                                         " misprediction at %s\n",
 199                                         tid, inst->pcState());
 200                             }
 201
 202                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
 203                                     "fetch to %s.\n", tid,
 204                                     inst->readPredTarg());
 205
 206                         } else if (inst->isIndirectCtrl()){
 207                             TheISA::PCState pc = inst->pcState();
 208                             TheISA::advancePC(pc, inst->staticInst);
 209                             inst->seqNum = seq_num;
 210                             inst->setPredTarg(pc);
 211
 212                             inst->bdelaySeqNum = seq_num;
 213
 214                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
 215                                     " fetch to %s.\n", tid,
 216                                     inst->readPredTarg());
 217                         } else {
 218                             panic("Non-control instruction (%s) mispredict"
 219                                   "ing?!!", inst->staticInst->getName());
 220                         }
 221
 222                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
 223                                 "start from stage %i.\n", tid, stage_num);
 224
 225                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
 226                                                                          tid);
 227
 228                         inst->squashingStage = stage_num;
 229
 230                         // Squash throughout other resources
 231                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
 232                                                     ResourcePool::SquashAll,
 233                                                     inst, 0, 0, tid);
 234
 235                         if (inst->predTaken()) {
 236                             predictedTakenIncorrect++;
 237                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 238                                     "PC %s ... Mispredicts! (Taken)\n",
 239                                     tid, inst->seqNum,
 240                                     inst->staticInst->disassemble(
 241                                         inst->instAddr()),
 242                                     inst->pcState());
 243                         } else {
 244                             predictedNotTakenIncorrect++;
 245                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 246                                     "PC %s ... Mispredicts! (Not Taken)\n",
 247                                     tid, inst->seqNum,
 248                                     inst->staticInst->disassemble(
 249                                         inst->instAddr()),
 250                                     inst->pcState());
 251                         }
 252                         predictedIncorrect++;
 253                     } else {
 254                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 255                                 "Correct.\n", inst->readTid(), seq_num);
 256                         predictedCorrect++;
 257                     }
 258
 259                     exec_req->done();
 260                 } else {
 261                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 262
 263                     exec_req->done();
 264                 }
 265             } else {
 266                 // Regular ALU instruction
 267                 fault = inst->execute();
 268                 executions++;
 269
 270                 if (fault == NoFault) {
 271                     inst->setExecuted();
 272
 273                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
 274                             "of execution is 0x%x.\n", inst->readTid(),
 275                             seq_num,
 276                             (inst->resultType(0) == InOrderDynInst::Float) ?
 277                             inst->readFloatResult(0) : inst->readIntResult(0));
 278                 } else {
 279                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 280                             "fault.\n", inst->readTid(), seq_num, fault->name());
 281                     inst->fault = fault;
 282                 }
 283
 284                 exec_req->done();
 285             }
 286         }
 287         break;
 288
 289       default:
 290         fatal("Unrecognized command to %s", resName);
 291     }
 292 }
 293
 294