src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  43     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  44 { }
  45
  46 void
  47 ExecutionUnit::regStats()
  48 {
  49     predictedTakenIncorrect
  50         .name(name() + ".predictedTakenIncorrect")
  51         .desc("Number of Branches Incorrectly Predicted As Taken.");
  52
  53     predictedNotTakenIncorrect
  54         .name(name() + ".predictedNotTakenIncorrect")
  55         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  56
  57     lastExecuteCycle = curTick;
  58
  59     cyclesExecuted
  60         .name(name() + ".cyclesExecuted")
  61         .desc("Number of Cycles Execution Unit was used.");
  62
  63     utilization
  64         .name(name() + ".utilization")
  65         .desc("Utilization of Execution Unit (cycles / totalCycles).");
  66     utilization = cyclesExecuted / cpu->numCycles;
  67
  68     Resource::regStats();
  69 }
  70
  71 void
  72 ExecutionUnit::execute(int slot_num)
  73 {
  74     ResourceRequest* exec_req = reqMap[slot_num];
  75     DynInstPtr inst = reqMap[slot_num]->inst;
  76     Fault fault = reqMap[slot_num]->fault;
  77     ThreadID tid = inst->readTid();
  78     int seq_num = inst->seqNum;
  79
  80     exec_req->fault = NoFault;
  81
  82     DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
  83             tid, seq_num, inst->readPC(), inst->instName());
  84
  85     switch (exec_req->cmd)
  86     {
  87       case ExecuteInst:
  88         {
  89             if (curTick != lastExecuteCycle) {
  90                 lastExecuteCycle = curTick;
  91                 cyclesExecuted++;
  92             }
  93
  94
  95             if (inst->isMemRef()) {
  96                 panic("%s not configured to handle memory ops.\n", resName);
  97             } else if (inst->isControl()) {
  98                 // Evaluate Branch
  99                 fault = inst->execute();
 100
 101                 inst->setExecuted();
 102
 103                 if (fault == NoFault) {
 104                     // If branch is mispredicted, then signal squash
 105                     // throughout all stages behind the pipeline stage
 106                     // that got squashed.
 107                     if (inst->mispredicted()) {
 108                         int stage_num = exec_req->getStageNum();
 109                         ThreadID tid = inst->readTid();
 110
 111                         // If it's a branch ...
 112                         if (inst->isDirectCtrl()) {
 113                             assert(!inst->isIndirectCtrl());
 114
 115                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 116                                 inst->bdelaySeqNum = seq_num;
 117                                 inst->setPredTarg(inst->nextPC);
 118
 119                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst"
 120                                         "[sn:%i] PC %#x mispredicted as taken.\n", tid,
 121                                         seq_num, inst->PC);
 122                             } else if (!inst->predTaken() && inst->isCondDelaySlot()) {
 123                                 inst->bdelaySeqNum = seq_num;
 124                                 inst->setPredTarg(inst->nextPC);
 125                                 inst->procDelaySlotOnMispred = true;
 126
 127                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst."
 128                                         "[sn:%i] PC %#x mispredicted as not taken.\n", tid,
 129                                         seq_num, inst->PC);
 130                             } else {
 131 #if ISA_HAS_DELAY_SLOT
 132                                 inst->bdelaySeqNum = seq_num + 1;
 133                                 inst->setPredTarg(inst->nextNPC);
 134 #else
 135                                 inst->bdelaySeqNum = seq_num;
 136                                 inst->setPredTarg(inst->nextPC);
 137 #endif
 138                                 DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at "
 139                                         "[sn:%i] PC %#x,\n\t squashing after delay slot "
 140                                         "instruction [sn:%i].\n",
 141                                         tid, seq_num, inst->PC, inst->bdelaySeqNum);
 142                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch "
 143                                         "misprediction at %#x\n", tid, inst->PC);
 144                             }
 145
 146                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
 147                                     inst->readPredTarg());
 148
 149                         } else if(inst->isIndirectCtrl()){
 150 #if ISA_HAS_DELAY_SLOT
 151                             inst->setPredTarg(inst->nextNPC);
 152                             inst->bdelaySeqNum = seq_num + 1;
 153 #else
 154                             inst->setPredTarg(inst->nextPC);
 155                             inst->bdelaySeqNum = seq_num;
 156 #endif
 157
 158                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
 159                                     inst->readPredTarg());
 160                         } else {
 161                             panic("Non-control instruction (%s) mispredicting?!!",
 162                                   inst->staticInst->getName());
 163                         }
 164
 165                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will start from stage %i.\n",
 166                                 tid, stage_num);
 167
 168                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 169
 170                         inst->squashingStage = stage_num;
 171
 172                         // Squash throughout other resources
 173                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 174                                                     inst, 0, 0, tid);
 175
 176                         if (inst->predTaken()) {
 177                             predictedTakenIncorrect++;
 178                         } else {
 179                             predictedNotTakenIncorrect++;
 180                         }
 181                     } else {
 182                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
 183                                 inst->readTid(), seq_num);
 184                     }
 185
 186                     exec_req->done();
 187                 } else {
 188                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 189                 }
 190             } else {
 191                 // Regular ALU instruction
 192                 fault = inst->execute();
 193
 194                 if (fault == NoFault) {
 195                     inst->setExecuted();
 196
 197                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
 198                             inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
 199                             inst->readFloatResult(0) : inst->readIntResult(0));
 200
 201                     exec_req->done();
 202                 } else {
 203                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 204                     cpu->trap(fault, tid);
 205                 }
 206             }
 207         }
 208         break;
 209
 210       default:
 211         fatal("Unrecognized command to %s", resName);
 212     }
 213 }
 214
 215