src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "cpu/inorder/resources/execution_unit.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/resource_pool.hh"
  38 #include "debug/InOrderExecute.hh"
  39 #include "debug/InOrderStall.hh"
  40
  41 using namespace std;
  42 using namespace ThePipeline;
  43
  44 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  45                              int res_latency, InOrderCPU *_cpu,
  46                              ThePipeline::Params *params)
  47     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  48       lastExecuteTick(0), lastControlTick(0), serializeTick(0)
  49 { }
  50
  51 void
  52 ExecutionUnit::regStats()
  53 {
  54     predictedTakenIncorrect
  55         .name(name() + ".predictedTakenIncorrect")
  56         .desc("Number of Branches Incorrectly Predicted As Taken.");
  57
  58     predictedNotTakenIncorrect
  59         .name(name() + ".predictedNotTakenIncorrect")
  60         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  61
  62     executions
  63         .name(name() + ".executions")
  64         .desc("Number of Instructions Executed.");
  65
  66
  67     predictedIncorrect
  68         .name(name() + ".mispredicted")
  69         .desc("Number of Branches Incorrectly Predicted");
  70
  71     predictedCorrect
  72         .name(name() + ".predicted")
  73         .desc("Number of Branches Incorrectly Predicted");
  74
  75     mispredictPct
  76         .name(name() + ".mispredictPct")
  77         .desc("Percentage of Incorrect Branches Predicts")
  78         .precision(6);
  79     mispredictPct = (predictedIncorrect /
  80                      (predictedCorrect + predictedIncorrect)) * 100;
  81
  82     Resource::regStats();
  83 }
  84
  85 void
  86 ExecutionUnit::execute(int slot_num)
  87 {
  88     ResourceRequest* exec_req = reqs[slot_num];
  89     DynInstPtr inst = reqs[slot_num]->inst;
  90     Fault fault = NoFault;
  91     InstSeqNum seq_num = inst->seqNum;
  92     Tick cur_tick = curTick();
  93
  94     if (cur_tick == serializeTick) {
  95         DPRINTF(InOrderExecute, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
  96                 "All instructions are being serialized this cycle\n",
  97                 inst->readTid(), seq_num, inst->pcState(), inst->instName());
  98         exec_req->done(false);
  99         return;
 100     }
 101
 102     switch (exec_req->cmd)
 103     {
 104       case ExecuteInst:
 105         {
 106             if (inst->isNop()) {
 107                 DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
 108                         "of %s.\n", inst->readTid(), seq_num, inst->pcState(),
 109                         inst->instName());
 110                 inst->setExecuted();
 111                 exec_req->done();
 112                 return;
 113             } else {
 114                 DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 115                         inst->readTid(), seq_num, inst->pcState(), inst->instName());
 116             }
 117
 118             if (cur_tick != lastExecuteTick) {
 119                 lastExecuteTick = cur_tick;
 120             }
 121
 122             assert(!inst->isMemRef());
 123
 124             if (inst->isSerializeAfter()) {
 125                 serializeTick = cur_tick;
 126                 DPRINTF(InOrderExecute, "Serializing execution after [tid:%i] "
 127                         "[sn:%i] [PC:%s] %s.\n", inst->readTid(), seq_num,
 128                         inst->pcState(), inst->instName());
 129             }
 130
 131             if (inst->isControl()) {
 132                 if (lastControlTick == cur_tick) {
 133                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 134                             "Inst Per Cycle. Blocking Request.\n");
 135                     exec_req->done(false);
 136                     return;
 137                 }
 138                 lastControlTick = curTick();
 139
 140                 // Evaluate Branch
 141                 fault = inst->execute();
 142                 executions++;
 143                 inst->setExecuted();
 144
 145                 if (fault == NoFault) {
 146                     // If branch is mispredicted, then signal squash
 147                     // throughout all stages behind the pipeline stage
 148                     // that got squashed.
 149                     if (inst->mispredicted()) {
 150                         int stage_num = exec_req->getStageNum();
 151                         ThreadID tid = inst->readTid();
 152                         // If it's a branch ...
 153                         if (inst->isDirectCtrl()) {
 154                             assert(!inst->isIndirectCtrl());
 155
 156                             TheISA::PCState pc = inst->pcState();
 157                             TheISA::advancePC(pc, inst->staticInst);
 158                             inst->setPredTarg(pc);
 159
 160                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 161                                 assert(0 && "Not Handling Conditional Delay Slots (1)");
 162                                 inst->bdelaySeqNum = seq_num;
 163                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 164                                         " branch inst [sn:%i] PC %s mis"
 165                                         "predicted as taken.\n", tid,
 166                                         seq_num, inst->pcState());
 167                             } else if (!inst->predTaken() && inst->isCondDelaySlot()) {
 168                                 assert(0 && "Not Handling Conditional Delay Slots (2)");
 169                                 inst->bdelaySeqNum = seq_num;
 170                                 inst->procDelaySlotOnMispred = true;
 171
 172                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 173                                         " branch inst [sn:%i] PC %s mis"
 174                                         "predicted as not taken.\n", tid,
 175                                         seq_num, inst->pcState());
 176                             } else {
 177                                 inst->bdelaySeqNum = seq_num;
 178
 179                                 DPRINTF(InOrderExecute, "[tid:%i]: "
 180                                         "Misprediction detected at "
 181                                         "[sn:%i] PC %s,\n\t squashing after "
 182                                         "delay slot instruction [sn:%i].\n",
 183                                         tid, seq_num, inst->pcState(),
 184                                         inst->bdelaySeqNum);
 185                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 186                                         " misprediction at %s\n",
 187                                         tid, inst->pcState());
 188                             }
 189
 190                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
 191                                     "fetch to %s.\n", tid,
 192                                     inst->readPredTarg());
 193
 194                         } else if (inst->isIndirectCtrl()){
 195                             TheISA::PCState pc = inst->pcState();
 196                             TheISA::advancePC(pc, inst->staticInst);
 197                             inst->seqNum = seq_num;
 198                             inst->setPredTarg(pc);
 199
 200                             inst->bdelaySeqNum = seq_num;
 201
 202                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
 203                                     " fetch to %s.\n", tid,
 204                                     inst->readPredTarg());
 205                         } else {
 206                             panic("Non-control instruction (%s) mispredict"
 207                                   "ing?!!", inst->staticInst->getName());
 208                         }
 209
 210                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
 211                                 "start from stage %i.\n", tid, stage_num);
 212
 213                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
 214                                                                          tid);
 215
 216                         inst->squashingStage = stage_num;
 217
 218                         // Squash throughout other resources
 219                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
 220                                                     ResourcePool::SquashAll,
 221                                                     inst, 0, 0, tid);
 222
 223                         if (inst->predTaken()) {
 224                             predictedTakenIncorrect++;
 225                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 226                                     "PC %s ... Mispredicts! (Taken)\n",
 227                                     tid, inst->seqNum,
 228                                     inst->staticInst->disassemble(
 229                                         inst->instAddr()),
 230                                     inst->pcState());
 231                         } else {
 232                             predictedNotTakenIncorrect++;
 233                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 234                                     "PC %s ... Mispredicts! (Not Taken)\n",
 235                                     tid, inst->seqNum,
 236                                     inst->staticInst->disassemble(
 237                                         inst->instAddr()),
 238                                     inst->pcState());
 239                         }
 240                         predictedIncorrect++;
 241                     } else {
 242                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 243                                 "Correct.\n", inst->readTid(), seq_num);
 244                         predictedCorrect++;
 245                     }
 246
 247                     exec_req->done();
 248                 } else {
 249                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 250
 251                     exec_req->done();
 252                 }
 253             } else {
 254                 // Regular ALU instruction
 255                 fault = inst->execute();
 256                 executions++;
 257
 258                 if (fault == NoFault) {
 259                     inst->setExecuted();
 260
 261                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
 262                             "of execution is 0x%x.\n", inst->readTid(),
 263                             seq_num,
 264                             (inst->resultType(0) == InOrderDynInst::Float) ?
 265                             inst->readFloatResult(0) : inst->readIntResult(0));
 266                 } else {
 267                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 268                             "fault.\n", inst->readTid(), seq_num, fault->name());
 269                     inst->fault = fault;
 270                 }
 271
 272                 exec_req->done();
 273             }
 274         }
 275         break;
 276
 277       default:
 278         fatal("Unrecognized command to %s", resName);
 279     }
 280 }
 281
 282