src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "cpu/inorder/resources/execution_unit.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/resource_pool.hh"
  38 #include "debug/InOrderExecute.hh"
  39 #include "debug/InOrderStall.hh"
  40
  41 using namespace std;
  42 using namespace ThePipeline;
  43
  44 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  45                              int res_latency, InOrderCPU *_cpu,
  46                              ThePipeline::Params *params)
  47     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  48       lastExecuteTick(0), lastControlTick(0), serializeTick(0)
  49 { }
  50
  51 void
  52 ExecutionUnit::regStats()
  53 {
  54     predictedTakenIncorrect
  55         .name(name() + ".predictedTakenIncorrect")
  56         .desc("Number of Branches Incorrectly Predicted As Taken.");
  57
  58     predictedNotTakenIncorrect
  59         .name(name() + ".predictedNotTakenIncorrect")
  60         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  61
  62     executions
  63         .name(name() + ".executions")
  64         .desc("Number of Instructions Executed.");
  65
  66
  67     predictedIncorrect
  68         .name(name() + ".mispredicted")
  69         .desc("Number of Branches Incorrectly Predicted");
  70
  71     predictedCorrect
  72         .name(name() + ".predicted")
  73         .desc("Number of Branches Incorrectly Predicted");
  74
  75     mispredictPct
  76         .name(name() + ".mispredictPct")
  77         .desc("Percentage of Incorrect Branches Predicts")
  78         .precision(6);
  79     mispredictPct = (predictedIncorrect /
  80                      (predictedCorrect + predictedIncorrect)) * 100;
  81
  82     Resource::regStats();
  83 }
  84
  85 void
  86 ExecutionUnit::execute(int slot_num)
  87 {
  88     ResourceRequest* exec_req = reqs[slot_num];
  89     DynInstPtr inst = reqs[slot_num]->inst;
  90     if (inst->fault != NoFault) {
  91         DPRINTF(InOrderExecute,
  92                 "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
  93                 "next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(),
  94                 inst->pcState());
  95         exec_req->done();
  96         return;
  97     }
  98
  99     Fault fault = NoFault;
 100     Tick cur_tick = curTick();
 101     unsigned stage_num = exec_req->getStageNum();
 102     ThreadID tid = inst->readTid();
 103 #if TRACING_ON
 104     InstSeqNum seq_num = inst->seqNum;
 105 #endif
 106     if (cur_tick == serializeTick) {
 107         DPRINTF(InOrderExecute, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
 108                 "All instructions are being serialized this cycle\n",
 109                 inst->readTid(), seq_num, inst->pcState(), inst->instName());
 110         exec_req->done(false);
 111         return;
 112     }
 113
 114     switch (exec_req->cmd)
 115     {
 116       case ExecuteInst:
 117         {
 118             if (inst->isNop()) {
 119                 DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
 120                         "of %s.\n", inst->readTid(), seq_num, inst->pcState(),
 121                         inst->instName());
 122                 inst->setExecuted();
 123                 exec_req->done();
 124                 return;
 125             } else {
 126                 DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 127                         inst->readTid(), seq_num, inst->pcState(), inst->instName());
 128             }
 129
 130             if (cur_tick != lastExecuteTick) {
 131                 lastExecuteTick = cur_tick;
 132             }
 133
 134             assert(!inst->isMemRef());
 135
 136             if (inst->isSerializeAfter()) {
 137                 serializeTick = cur_tick;
 138                 DPRINTF(InOrderExecute, "Serializing execution after [tid:%i] "
 139                         "[sn:%i] [PC:%s] %s.\n", inst->readTid(), seq_num,
 140                         inst->pcState(), inst->instName());
 141             }
 142
 143             if (inst->isControl()) {
 144                 if (lastControlTick == cur_tick) {
 145                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 146                             "Inst Per Cycle. Blocking Request.\n");
 147                     exec_req->done(false);
 148                     return;
 149                 }
 150                 lastControlTick = curTick();
 151
 152                 // Evaluate Branch
 153                 fault = inst->execute();
 154
 155                 // Should unconditional control , pc relative count as an
 156                 // execution??? Probably not.
 157                 executions++;
 158
 159                 if (fault == NoFault) {
 160                     inst->setExecuted();
 161
 162                     if (inst->mispredicted()) {
 163                         assert(inst->isControl());
 164
 165                         // Set up Squash Generated By this Misprediction
 166                         TheISA::PCState pc = inst->pcState();
 167                         TheISA::advancePC(pc, inst->staticInst);
 168                         inst->setPredTarg(pc);
 169                         inst->setSquashInfo(stage_num);
 170                         setupSquash(inst, stage_num, tid);
 171
 172                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i] Squashing from "
 173                                 "stage %i. Redirecting  fetch to %s.\n", tid,
 174                                 inst->seqNum, stage_num, pc);
 175                         DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 176                                 " misprediction at %s\n", tid, inst->pcState());
 177
 178                         if (inst->predTaken()) {
 179                             predictedTakenIncorrect++;
 180                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 181                                     "PC %s ... Mispredicts! "
 182                                     "(Prediction: Taken)\n",
 183                                     tid, inst->seqNum,
 184                                     inst->staticInst->disassemble(
 185                                         inst->instAddr()),
 186                                     inst->pcState());
 187                         } else {
 188                             predictedNotTakenIncorrect++;
 189                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 190                                     "PC %s ... Mispredicts! "
 191                                     "(Prediction: Not Taken)\n",
 192                                     tid, inst->seqNum,
 193                                     inst->staticInst->disassemble(
 194                                         inst->instAddr()),
 195                                     inst->pcState());
 196                         }
 197                         predictedIncorrect++;
 198                     } else {
 199                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 200                                 "Correct.\n", inst->readTid(), seq_num);
 201                         predictedCorrect++;
 202                     }
 203
 204                     exec_req->done();
 205                 } else {
 206                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 207                             inst->readTid(), inst->seqNum, fault->name());
 208                     inst->fault = fault;
 209                     exec_req->done();
 210                 }
 211             } else {
 212                 // Regular ALU instruction
 213                 fault = inst->execute();
 214                 executions++;
 215
 216                 if (fault == NoFault) {
 217                     inst->setExecuted();
 218
 219 #if TRACING_ON
 220                     for (int didx = 0; didx < inst->numDestRegs(); didx++)
 221                         if (inst->resultType(didx) == InOrderDynInst::Float ||
 222                             inst->resultType(didx) == InOrderDynInst::Double)
 223                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 224                                     "of FP execution is %08f (%x).\n", inst->readTid(),
 225                                     seq_num, didx, inst->readFloatResult(didx),
 226                                     inst->readIntResult(didx));
 227                         else
 228                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 229                                     "of Int execution is 0x%x.\n", inst->readTid(),
 230                                     seq_num, didx, inst->readIntResult(didx));
 231 #endif
 232
 233 #if !FULL_SYSTEM
 234                     // The Syscall might change the PC, so conservatively
 235                     // squash everything behing it
 236                     if (inst->isSyscall()) {
 237                         inst->setSquashInfo(stage_num);
 238                         setupSquash(inst, stage_num, tid);
 239                     }
 240 #endif
 241                 } else {
 242                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 243                             "fault.\n", inst->readTid(), seq_num, fault->name());
 244                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 245                             inst->readTid(), inst->seqNum, fault->name());
 246                     inst->fault = fault;
 247                 }
 248
 249                 exec_req->done();
 250             }
 251         }
 252         break;
 253
 254       default:
 255         fatal("Unrecognized command to %s", resName);
 256     }
 257 }
 258
 259