2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "cpu/inorder/resources/execution_unit.hh"
35 #include "cpu/inorder/resource_pool.hh"
36 #include "cpu/inorder/cpu.hh"
39 using namespace ThePipeline
;
41 ExecutionUnit::ExecutionUnit(string res_name
, int res_id
, int res_width
,
42 int res_latency
, InOrderCPU
*_cpu
,
43 ThePipeline::Params
*params
)
44 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
),
45 lastExecuteTick(0), lastControlTick(0), serializeTick(0)
49 ExecutionUnit::regStats()
51 predictedTakenIncorrect
52 .name(name() + ".predictedTakenIncorrect")
53 .desc("Number of Branches Incorrectly Predicted As Taken.");
55 predictedNotTakenIncorrect
56 .name(name() + ".predictedNotTakenIncorrect")
57 .desc("Number of Branches Incorrectly Predicted As Not Taken).");
60 .name(name() + ".executions")
61 .desc("Number of Instructions Executed.");
65 .name(name() + ".mispredicted")
66 .desc("Number of Branches Incorrectly Predicted");
69 .name(name() + ".predicted")
70 .desc("Number of Branches Incorrectly Predicted");
73 .name(name() + ".mispredictPct")
74 .desc("Percentage of Incorrect Branches Predicts")
76 mispredictPct
= (predictedIncorrect
/
77 (predictedCorrect
+ predictedIncorrect
)) * 100;
83 ExecutionUnit::execute(int slot_num
)
85 ResourceRequest
* exec_req
= reqs
[slot_num
];
86 DynInstPtr inst
= reqs
[slot_num
]->inst
;
87 Fault fault
= NoFault
;
88 int seq_num
= inst
->seqNum
;
89 Tick cur_tick
= curTick();
91 if (cur_tick
== serializeTick
) {
92 DPRINTF(InOrderExecute
, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
93 "All instructions are being serialized this cycle\n",
94 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
95 exec_req
->done(false);
100 switch (exec_req
->cmd
)
105 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
106 "of %s.\n", inst
->readTid(), seq_num
, inst
->pcState(),
112 DPRINTF(InOrderExecute
, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
113 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
116 if (cur_tick
!= lastExecuteTick
) {
117 lastExecuteTick
= cur_tick
;
120 assert(!inst
->isMemRef());
122 if (inst
->isSerializeAfter()) {
123 serializeTick
= cur_tick
;
124 DPRINTF(InOrderExecute
, "Serializing execution after [tid:%i] "
125 "[sn:%i] [PC:%s] %s.\n", inst
->readTid(), seq_num
,
126 inst
->pcState(), inst
->instName());
129 if (inst
->isControl()) {
130 if (lastControlTick
== cur_tick
) {
131 DPRINTF(InOrderExecute
, "Can not Execute More than One Control "
132 "Inst Per Cycle. Blocking Request.\n");
133 exec_req
->done(false);
136 lastControlTick
= curTick();
139 fault
= inst
->execute();
144 if (fault
== NoFault
) {
145 // If branch is mispredicted, then signal squash
146 // throughout all stages behind the pipeline stage
147 // that got squashed.
148 if (inst
->mispredicted()) {
149 int stage_num
= exec_req
->getStageNum();
150 ThreadID tid
= inst
->readTid();
151 // If it's a branch ...
152 if (inst
->isDirectCtrl()) {
153 assert(!inst
->isIndirectCtrl());
155 TheISA::PCState pc
= inst
->pcState();
156 TheISA::advancePC(pc
, inst
->staticInst
);
157 inst
->setPredTarg(pc
);
159 if (inst
->predTaken() && inst
->isCondDelaySlot()) {
160 inst
->bdelaySeqNum
= seq_num
;
162 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
163 " branch inst [sn:%i] PC %s mis"
164 "predicted as taken.\n", tid
,
165 seq_num
, inst
->pcState());
166 } else if (!inst
->predTaken() &&
167 inst
->isCondDelaySlot()) {
168 inst
->bdelaySeqNum
= seq_num
;
169 inst
->procDelaySlotOnMispred
= true;
171 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
172 " branch inst [sn:%i] PC %s mis"
173 "predicted as not taken.\n", tid
,
174 seq_num
, inst
->pcState());
176 #if ISA_HAS_DELAY_SLOT
177 inst
->bdelaySeqNum
= seq_num
+ 1;
179 inst
->bdelaySeqNum
= seq_num
;
181 DPRINTF(InOrderExecute
, "[tid:%i]: "
182 "Misprediction detected at "
183 "[sn:%i] PC %s,\n\t squashing after "
184 "delay slot instruction [sn:%i].\n",
185 tid
, seq_num
, inst
->pcState(),
187 DPRINTF(InOrderStall
, "STALL: [tid:%i]: Branch"
188 " misprediction at %s\n",
189 tid
, inst
->pcState());
192 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting "
193 "fetch to %s.\n", tid
,
194 inst
->readPredTarg());
196 } else if (inst
->isIndirectCtrl()){
197 TheISA::PCState pc
= inst
->pcState();
198 TheISA::advancePC(pc
, inst
->staticInst
);
199 inst
->seqNum
= seq_num
;
200 inst
->setPredTarg(pc
);
202 #if ISA_HAS_DELAY_SLOT
203 inst
->bdelaySeqNum
= seq_num
+ 1;
205 inst
->bdelaySeqNum
= seq_num
;
208 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting"
209 " fetch to %s.\n", tid
,
210 inst
->readPredTarg());
212 panic("Non-control instruction (%s) mispredict"
213 "ing?!!", inst
->staticInst
->getName());
216 DPRINTF(InOrderExecute
, "[tid:%i] Squashing will "
217 "start from stage %i.\n", tid
, stage_num
);
219 cpu
->pipelineStage
[stage_num
]->squashDueToBranch(inst
,
222 inst
->squashingStage
= stage_num
;
224 // Squash throughout other resources
225 cpu
->resPool
->scheduleEvent((InOrderCPU::CPUEventType
)
226 ResourcePool::SquashAll
,
229 if (inst
->predTaken()) {
230 predictedTakenIncorrect
++;
231 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
232 "PC %s ... Mispredicts! (Taken)\n",
234 inst
->staticInst
->disassemble(
238 predictedNotTakenIncorrect
++;
239 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
240 "PC %s ... Mispredicts! (Not Taken)\n",
242 inst
->staticInst
->disassemble(
246 predictedIncorrect
++;
248 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: Prediction"
249 "Correct.\n", inst
->readTid(), seq_num
);
255 warn("inst [sn:%i] had a %s fault",
256 seq_num
, fault
->name());
259 // Regular ALU instruction
260 fault
= inst
->execute();
263 if (fault
== NoFault
) {
266 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: The result "
267 "of execution is 0x%x.\n", inst
->readTid(),
269 (inst
->resultType(0) == InOrderDynInst::Float
) ?
270 inst
->readFloatResult(0) : inst
->readIntResult(0));
272 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: had a %s "
273 "fault.\n", inst
->readTid(), seq_num
, fault
->name());
283 fatal("Unrecognized command to %s", resName
);