2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "cpu/inorder/resources/execution_unit.hh"
35 #include "cpu/inorder/resource_pool.hh"
36 #include "cpu/inorder/cpu.hh"
39 using namespace ThePipeline
;
41 ExecutionUnit::ExecutionUnit(string res_name
, int res_id
, int res_width
,
42 int res_latency
, InOrderCPU
*_cpu
,
43 ThePipeline::Params
*params
)
44 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
)
48 ExecutionUnit::regStats()
50 predictedTakenIncorrect
51 .name(name() + ".predictedTakenIncorrect")
52 .desc("Number of Branches Incorrectly Predicted As Taken.");
54 predictedNotTakenIncorrect
55 .name(name() + ".predictedNotTakenIncorrect")
56 .desc("Number of Branches Incorrectly Predicted As Not Taken).");
58 lastExecuteCycle
= curTick
;
61 .name(name() + ".executions")
62 .desc("Number of Instructions Executed.");
66 .name(name() + ".mispredicted")
67 .desc("Number of Branches Incorrectly Predicted");
70 .name(name() + ".predicted")
71 .desc("Number of Branches Incorrectly Predicted");
74 .name(name() + ".mispredictPct")
75 .desc("Percentage of Incorrect Branches Predicts")
77 mispredictPct
= (predictedIncorrect
/
78 (predictedCorrect
+ predictedIncorrect
)) * 100;
84 ExecutionUnit::execute(int slot_num
)
86 ResourceRequest
* exec_req
= reqMap
[slot_num
];
87 DynInstPtr inst
= reqMap
[slot_num
]->inst
;
88 Fault fault
= reqMap
[slot_num
]->fault
;
89 ThreadID tid
= inst
->readTid();
90 int seq_num
= inst
->seqNum
;
92 exec_req
->fault
= NoFault
;
94 DPRINTF(InOrderExecute
, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
95 tid
, seq_num
, inst
->readPC(), inst
->instName());
97 switch (exec_req
->cmd
)
101 if (curTick
!= lastExecuteCycle
) {
102 lastExecuteCycle
= curTick
;
106 if (inst
->isMemRef()) {
107 panic("%s not configured to handle memory ops.\n", resName
);
108 } else if (inst
->isControl()) {
110 fault
= inst
->execute();
115 if (fault
== NoFault
) {
116 // If branch is mispredicted, then signal squash
117 // throughout all stages behind the pipeline stage
118 // that got squashed.
119 if (inst
->mispredicted()) {
120 int stage_num
= exec_req
->getStageNum();
121 ThreadID tid
= inst
->readTid();
123 // If it's a branch ...
124 if (inst
->isDirectCtrl()) {
125 assert(!inst
->isIndirectCtrl());
127 if (inst
->predTaken() && inst
->isCondDelaySlot()) {
128 inst
->bdelaySeqNum
= seq_num
;
129 inst
->setPredTarg(inst
->nextPC
);
131 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
132 " branch inst [sn:%i] PC %#x mis"
133 "predicted as taken.\n", tid
,
135 } else if (!inst
->predTaken() &&
136 inst
->isCondDelaySlot()) {
137 inst
->bdelaySeqNum
= seq_num
;
138 inst
->setPredTarg(inst
->nextPC
);
139 inst
->procDelaySlotOnMispred
= true;
141 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
142 " branch inst [sn:%i] PC %#x mis"
143 "predicted as not taken.\n", tid
,
146 #if ISA_HAS_DELAY_SLOT
147 inst
->bdelaySeqNum
= seq_num
+ 1;
148 inst
->setPredTarg(inst
->nextNPC
);
150 inst
->bdelaySeqNum
= seq_num
;
151 inst
->setPredTarg(inst
->nextPC
);
153 DPRINTF(InOrderExecute
, "[tid:%i]: "
154 "Misprediction detected at "
155 "[sn:%i] PC %#x,\n\t squashing after "
156 "delay slot instruction [sn:%i].\n",
157 tid
, seq_num
, inst
->PC
,
159 DPRINTF(InOrderStall
, "STALL: [tid:%i]: Branch"
160 " misprediction at %#x\n",
164 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting "
165 "fetch to %#x.\n", tid
,
166 inst
->readPredTarg());
168 } else if(inst
->isIndirectCtrl()){
169 #if ISA_HAS_DELAY_SLOT
170 inst
->setPredTarg(inst
->nextNPC
);
171 inst
->bdelaySeqNum
= seq_num
+ 1;
173 inst
->setPredTarg(inst
->nextPC
);
174 inst
->bdelaySeqNum
= seq_num
;
177 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting"
178 " fetch to %#x.\n", tid
,
179 inst
->readPredTarg());
181 panic("Non-control instruction (%s) mispredict"
182 "ing?!!", inst
->staticInst
->getName());
185 DPRINTF(InOrderExecute
, "[tid:%i] Squashing will "
186 "start from stage %i.\n", tid
, stage_num
);
188 cpu
->pipelineStage
[stage_num
]->squashDueToBranch(inst
,
191 inst
->squashingStage
= stage_num
;
193 // Squash throughout other resources
194 cpu
->resPool
->scheduleEvent((InOrderCPU::CPUEventType
)
195 ResourcePool::SquashAll
,
198 if (inst
->predTaken()) {
199 predictedTakenIncorrect
++;
200 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ... PC%#x ... Mispredicts! (Taken)\n",
201 tid
, inst
->seqNum
, inst
->staticInst
->disassemble(inst
->PC
),
204 predictedNotTakenIncorrect
++;
205 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ... PC%#x ... Mispredicts! (Not Taken)\n",
206 tid
, inst
->seqNum
, inst
->staticInst
->disassemble(inst
->PC
),
209 predictedIncorrect
++;
211 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: Prediction"
212 "Correct.\n", inst
->readTid(), seq_num
);
218 warn("inst [sn:%i] had a %s fault",
219 seq_num
, fault
->name());
222 // Regular ALU instruction
223 fault
= inst
->execute();
226 if (fault
== NoFault
) {
229 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: The result "
230 "of execution is 0x%x.\n", inst
->readTid(),
232 (inst
->resultType(0) == InOrderDynInst::Float
) ?
233 inst
->readFloatResult(0) : inst
->readIntResult(0));
237 warn("inst [sn:%i] had a %s fault",
238 seq_num
, fault
->name());
239 cpu
->trap(fault
, tid
, inst
);
246 fatal("Unrecognized command to %s", resName
);