src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                              int res_latency, InOrderCPU *_cpu,
  43                              ThePipeline::Params *params)
  44     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  45 { }
  46
  47 void
  48 ExecutionUnit::regStats()
  49 {
  50     predictedTakenIncorrect
  51         .name(name() + ".predictedTakenIncorrect")
  52         .desc("Number of Branches Incorrectly Predicted As Taken.");
  53
  54     predictedNotTakenIncorrect
  55         .name(name() + ".predictedNotTakenIncorrect")
  56         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  57
  58     lastExecuteCycle = curTick;
  59
  60     executions
  61         .name(name() + ".executions")
  62         .desc("Number of Instructions Executed.");
  63
  64
  65     predictedIncorrect
  66         .name(name() + ".mispredicted")
  67         .desc("Number of Branches Incorrectly Predicted");
  68
  69     predictedCorrect
  70         .name(name() + ".predicted")
  71         .desc("Number of Branches Incorrectly Predicted");
  72
  73     mispredictPct
  74         .name(name() + ".mispredictPct")
  75         .desc("Percentage of Incorrect Branches Predicts")
  76         .precision(6);
  77     mispredictPct = (predictedIncorrect /
  78                      (predictedCorrect + predictedIncorrect)) * 100;
  79
  80     Resource::regStats();
  81 }
  82
  83 void
  84 ExecutionUnit::execute(int slot_num)
  85 {
  86     ResourceRequest* exec_req = reqMap[slot_num];
  87     DynInstPtr inst = reqMap[slot_num]->inst;
  88     Fault fault = reqMap[slot_num]->fault;
  89     ThreadID tid = inst->readTid();
  90     int seq_num = inst->seqNum;
  91
  92     exec_req->fault = NoFault;
  93
  94     DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
  95             tid, seq_num, inst->pcState(), inst->instName());
  96
  97     switch (exec_req->cmd)
  98     {
  99       case ExecuteInst:
 100         {
 101             if (curTick != lastExecuteCycle) {
 102                 lastExecuteCycle = curTick;
 103             }
 104
 105
 106             if (inst->isMemRef()) {
 107                 panic("%s not configured to handle memory ops.\n", resName);
 108             } else if (inst->isControl()) {
 109                 // Evaluate Branch
 110                 fault = inst->execute();
 111                 executions++;
 112
 113                 inst->setExecuted();
 114
 115                 if (fault == NoFault) {
 116                     // If branch is mispredicted, then signal squash
 117                     // throughout all stages behind the pipeline stage
 118                     // that got squashed.
 119                     if (inst->mispredicted()) {
 120                         int stage_num = exec_req->getStageNum();
 121                         ThreadID tid = inst->readTid();
 122
 123                         // If it's a branch ...
 124                         if (inst->isDirectCtrl()) {
 125                             assert(!inst->isIndirectCtrl());
 126
 127                             TheISA::PCState pc = inst->pcState();
 128                             TheISA::advancePC(pc, inst->staticInst);
 129                             inst->setPredTarg(pc);
 130
 131                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 132                                 inst->bdelaySeqNum = seq_num;
 133
 134                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 135                                         " branch inst [sn:%i] PC %s mis"
 136                                         "predicted as taken.\n", tid,
 137                                         seq_num, inst->pcState());
 138                             } else if (!inst->predTaken() &&
 139                                        inst->isCondDelaySlot()) {
 140                                 inst->bdelaySeqNum = seq_num;
 141                                 inst->procDelaySlotOnMispred = true;
 142
 143                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 144                                         " branch inst [sn:%i] PC %s mis"
 145                                         "predicted as not taken.\n", tid,
 146                                         seq_num, inst->pcState());
 147                             } else {
 148 #if ISA_HAS_DELAY_SLOT
 149                                 inst->bdelaySeqNum = seq_num + 1;
 150 #else
 151                                 inst->bdelaySeqNum = seq_num;
 152 #endif
 153                                 DPRINTF(InOrderExecute, "[tid:%i]: "
 154                                         "Misprediction detected at "
 155                                         "[sn:%i] PC %s,\n\t squashing after "
 156                                         "delay slot instruction [sn:%i].\n",
 157                                         tid, seq_num, inst->pcState(),
 158                                         inst->bdelaySeqNum);
 159                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 160                                         " misprediction at %s\n",
 161                                         tid, inst->pcState());
 162                             }
 163
 164                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
 165                                     "fetch to %s.\n", tid,
 166                                     inst->readPredTarg());
 167
 168                         } else if (inst->isIndirectCtrl()){
 169                             TheISA::PCState pc = inst->pcState();
 170                             TheISA::advancePC(pc, inst->staticInst);
 171                             inst->seqNum = seq_num;
 172                             inst->setPredTarg(pc);
 173
 174 #if ISA_HAS_DELAY_SLOT
 175                             inst->bdelaySeqNum = seq_num + 1;
 176 #else
 177                             inst->bdelaySeqNum = seq_num;
 178 #endif
 179
 180                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
 181                                     " fetch to %s.\n", tid,
 182                                     inst->readPredTarg());
 183                         } else {
 184                             panic("Non-control instruction (%s) mispredict"
 185                                   "ing?!!", inst->staticInst->getName());
 186                         }
 187
 188                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
 189                                 "start from stage %i.\n", tid, stage_num);
 190
 191                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
 192                                                                          tid);
 193
 194                         inst->squashingStage = stage_num;
 195
 196                         // Squash throughout other resources
 197                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
 198                                                     ResourcePool::SquashAll,
 199                                                     inst, 0, 0, tid);
 200
 201                         if (inst->predTaken()) {
 202                             predictedTakenIncorrect++;
 203                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 204                                     "PC %s ... Mispredicts! (Taken)\n",
 205                                     tid, inst->seqNum,
 206                                     inst->staticInst->disassemble(
 207                                         inst->instAddr()),
 208                                     inst->pcState());
 209                         } else {
 210                             predictedNotTakenIncorrect++;
 211                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 212                                     "PC %s ... Mispredicts! (Not Taken)\n",
 213                                     tid, inst->seqNum,
 214                                     inst->staticInst->disassemble(
 215                                         inst->instAddr()),
 216                                     inst->pcState());
 217                         }
 218                         predictedIncorrect++;
 219                     } else {
 220                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 221                                 "Correct.\n", inst->readTid(), seq_num);
 222                         predictedCorrect++;
 223                     }
 224
 225                     exec_req->done();
 226                 } else {
 227                     warn("inst [sn:%i] had a %s fault",
 228                          seq_num, fault->name());
 229                 }
 230             } else {
 231                 // Regular ALU instruction
 232                 fault = inst->execute();
 233                 executions++;
 234
 235                 if (fault == NoFault) {
 236                     inst->setExecuted();
 237
 238                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
 239                             "of execution is 0x%x.\n", inst->readTid(),
 240                             seq_num,
 241                             (inst->resultType(0) == InOrderDynInst::Float) ?
 242                             inst->readFloatResult(0) : inst->readIntResult(0));
 243
 244                     exec_req->done();
 245                 } else {
 246                     warn("inst [sn:%i] had a %s fault",
 247                          seq_num, fault->name());
 248                     cpu->trap(fault, tid, inst);
 249                 }
 250             }
 251         }
 252         break;
 253
 254       default:
 255         fatal("Unrecognized command to %s", resName);
 256     }
 257 }
 258
 259