src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "cpu/inorder/resources/execution_unit.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/resource_pool.hh"
  38 #include "debug/InOrderExecute.hh"
  39 #include "debug/InOrderStall.hh"
  40
  41 using namespace std;
  42 using namespace ThePipeline;
  43
  44 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  45                              int res_latency, InOrderCPU *_cpu,
  46                              ThePipeline::Params *params)
  47     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  48       lastExecuteTick(0), lastControlTick(0)
  49 { }
  50
  51 void
  52 ExecutionUnit::regStats()
  53 {
  54     predictedTakenIncorrect
  55         .name(name() + ".predictedTakenIncorrect")
  56         .desc("Number of Branches Incorrectly Predicted As Taken.");
  57
  58     predictedNotTakenIncorrect
  59         .name(name() + ".predictedNotTakenIncorrect")
  60         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  61
  62     executions
  63         .name(name() + ".executions")
  64         .desc("Number of Instructions Executed.");
  65
  66
  67     predictedIncorrect
  68         .name(name() + ".mispredicted")
  69         .desc("Number of Branches Incorrectly Predicted");
  70
  71     predictedCorrect
  72         .name(name() + ".predicted")
  73         .desc("Number of Branches Incorrectly Predicted");
  74
  75     mispredictPct
  76         .name(name() + ".mispredictPct")
  77         .desc("Percentage of Incorrect Branches Predicts")
  78         .precision(6);
  79     mispredictPct = (predictedIncorrect /
  80                      (predictedCorrect + predictedIncorrect)) * 100;
  81
  82     Resource::regStats();
  83 }
  84
  85 void
  86 ExecutionUnit::execute(int slot_num)
  87 {
  88     ResourceRequest* exec_req = reqs[slot_num];
  89     DynInstPtr inst = reqs[slot_num]->inst;
  90     if (inst->fault != NoFault) {
  91         DPRINTF(InOrderExecute,
  92                 "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
  93                 "next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(),
  94                 inst->pcState());
  95         exec_req->done();
  96         return;
  97     }
  98
  99     Fault fault = NoFault;
 100     Tick cur_tick = curTick();
 101     unsigned stage_num = exec_req->getStageNum();
 102     ThreadID tid = inst->readTid();
 103 #if TRACING_ON
 104     InstSeqNum seq_num = inst->seqNum;
 105 #endif
 106
 107     switch (exec_req->cmd)
 108     {
 109       case ExecuteInst:
 110         {
 111             if (inst->isNop()) {
 112                 DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
 113                         "of %s.\n", inst->readTid(), seq_num, inst->pcState(),
 114                         inst->instName());
 115                 inst->setExecuted();
 116                 exec_req->done();
 117                 return;
 118             } else {
 119                 DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 120                         inst->readTid(), seq_num, inst->pcState(), inst->instName());
 121             }
 122
 123             if (cur_tick != lastExecuteTick) {
 124                 lastExecuteTick = cur_tick;
 125             }
 126
 127             //@todo: handle address generation here
 128             assert(!inst->isMemRef());
 129
 130             if (inst->isControl()) {
 131                 if (lastControlTick == cur_tick) {
 132                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 133                             "Inst Per Cycle. Blocking Request.\n");
 134                     exec_req->done(false);
 135                     return;
 136                 }
 137                 lastControlTick = curTick();
 138
 139                 // Evaluate Branch
 140                 fault = inst->execute();
 141
 142                 // Should unconditional control , pc relative count as an
 143                 // execution??? Probably not.
 144                 executions++;
 145
 146                 if (fault == NoFault) {
 147                     inst->setExecuted();
 148
 149                     if (inst->mispredicted()) {
 150                         assert(inst->isControl());
 151
 152                         // Set up Squash Generated By this Misprediction
 153                         TheISA::PCState pc = inst->pcState();
 154                         TheISA::advancePC(pc, inst->staticInst);
 155                         inst->setPredTarg(pc);
 156                         inst->setSquashInfo(stage_num);
 157                         setupSquash(inst, stage_num, tid);
 158
 159                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i] Squashing from "
 160                                 "stage %i. Redirecting  fetch to %s.\n", tid,
 161                                 inst->seqNum, stage_num, pc);
 162                         DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 163                                 " misprediction at %s\n", tid, inst->pcState());
 164
 165                         if (inst->predTaken()) {
 166                             predictedTakenIncorrect++;
 167                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 168                                     "PC %s ... Mispredicts! "
 169                                     "(Prediction: Taken)\n",
 170                                     tid, inst->seqNum,
 171                                     inst->staticInst->disassemble(
 172                                         inst->instAddr()),
 173                                     inst->pcState());
 174                         } else {
 175                             predictedNotTakenIncorrect++;
 176                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 177                                     "PC %s ... Mispredicts! "
 178                                     "(Prediction: Not Taken)\n",
 179                                     tid, inst->seqNum,
 180                                     inst->staticInst->disassemble(
 181                                         inst->instAddr()),
 182                                     inst->pcState());
 183                         }
 184                         predictedIncorrect++;
 185                     } else {
 186                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 187                                 "Correct.\n", inst->readTid(), seq_num);
 188                         predictedCorrect++;
 189                     }
 190
 191                     exec_req->done();
 192                 } else {
 193                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 194                             inst->readTid(), inst->seqNum, fault->name());
 195                     inst->fault = fault;
 196                     exec_req->done();
 197                 }
 198             } else {
 199                 // Regular ALU instruction
 200                 fault = inst->execute();
 201                 executions++;
 202
 203                 if (fault == NoFault) {
 204                     inst->setExecuted();
 205
 206 #if TRACING_ON
 207                     for (int didx = 0; didx < inst->numDestRegs(); didx++)
 208                         if (inst->resultType(didx) == InOrderDynInst::Float ||
 209                             inst->resultType(didx) == InOrderDynInst::FloatBits ||
 210                             inst->resultType(didx) == InOrderDynInst::Double)
 211                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 212                                     "of FP execution is %08f (%x).\n", inst->readTid(),
 213                                     seq_num, didx, inst->readFloatResult(didx),
 214                                     inst->readFloatBitsResult(didx));
 215                         else
 216                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 217                                     "of Int execution is 0x%x.\n", inst->readTid(),
 218                                     seq_num, didx, inst->readIntResult(didx));
 219 #endif
 220
 221 #if !FULL_SYSTEM
 222                     // The Syscall might change the PC, so conservatively
 223                     // squash everything behing it
 224                     if (inst->isSyscall()) {
 225                         inst->setSquashInfo(stage_num);
 226                         setupSquash(inst, stage_num, tid);
 227                     }
 228 #endif
 229                 } else {
 230                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 231                             "fault.\n", inst->readTid(), seq_num, fault->name());
 232                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 233                             inst->readTid(), inst->seqNum, fault->name());
 234                     inst->fault = fault;
 235                 }
 236
 237                 exec_req->done();
 238             }
 239         }
 240         break;
 241
 242       default:
 243         fatal("Unrecognized command to %s", resName);
 244     }
 245 }
 246
 247