2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
35 #include "cpu/inorder/resources/execution_unit.hh"
36 #include "cpu/inorder/cpu.hh"
37 #include "cpu/inorder/resource_pool.hh"
38 #include "debug/InOrderExecute.hh"
39 #include "debug/InOrderStall.hh"
42 using namespace ThePipeline
;
44 ExecutionUnit::ExecutionUnit(string res_name
, int res_id
, int res_width
,
45 int res_latency
, InOrderCPU
*_cpu
,
46 ThePipeline::Params
*params
)
47 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
),
48 lastExecuteTick(0), lastControlTick(0), serializeTick(0)
52 ExecutionUnit::regStats()
54 predictedTakenIncorrect
55 .name(name() + ".predictedTakenIncorrect")
56 .desc("Number of Branches Incorrectly Predicted As Taken.");
58 predictedNotTakenIncorrect
59 .name(name() + ".predictedNotTakenIncorrect")
60 .desc("Number of Branches Incorrectly Predicted As Not Taken).");
63 .name(name() + ".executions")
64 .desc("Number of Instructions Executed.");
68 .name(name() + ".mispredicted")
69 .desc("Number of Branches Incorrectly Predicted");
72 .name(name() + ".predicted")
73 .desc("Number of Branches Incorrectly Predicted");
76 .name(name() + ".mispredictPct")
77 .desc("Percentage of Incorrect Branches Predicts")
79 mispredictPct
= (predictedIncorrect
/
80 (predictedCorrect
+ predictedIncorrect
)) * 100;
86 ExecutionUnit::execute(int slot_num
)
88 ResourceRequest
* exec_req
= reqs
[slot_num
];
89 DynInstPtr inst
= reqs
[slot_num
]->inst
;
90 Fault fault
= NoFault
;
91 InstSeqNum seq_num
= inst
->seqNum
;
92 Tick cur_tick
= curTick();
94 if (cur_tick
== serializeTick
) {
95 DPRINTF(InOrderExecute
, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
96 "All instructions are being serialized this cycle\n",
97 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
98 exec_req
->done(false);
102 switch (exec_req
->cmd
)
107 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
108 "of %s.\n", inst
->readTid(), seq_num
, inst
->pcState(),
114 DPRINTF(InOrderExecute
, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
115 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
118 if (cur_tick
!= lastExecuteTick
) {
119 lastExecuteTick
= cur_tick
;
122 assert(!inst
->isMemRef());
124 if (inst
->isSerializeAfter()) {
125 serializeTick
= cur_tick
;
126 DPRINTF(InOrderExecute
, "Serializing execution after [tid:%i] "
127 "[sn:%i] [PC:%s] %s.\n", inst
->readTid(), seq_num
,
128 inst
->pcState(), inst
->instName());
131 if (inst
->isControl()) {
132 if (lastControlTick
== cur_tick
) {
133 DPRINTF(InOrderExecute
, "Can not Execute More than One Control "
134 "Inst Per Cycle. Blocking Request.\n");
135 exec_req
->done(false);
138 lastControlTick
= curTick();
141 fault
= inst
->execute();
144 if (fault
== NoFault
) {
147 if (inst
->mispredicted()) {
148 assert(inst
->isControl());
150 // Set up Squash Generated By this Misprediction
151 unsigned stage_num
= exec_req
->getStageNum();
152 ThreadID tid
= inst
->readTid();
153 TheISA::PCState pc
= inst
->pcState();
154 TheISA::advancePC(pc
, inst
->staticInst
);
155 inst
->setPredTarg(pc
);
156 inst
->setSquashInfo(stage_num
);
158 setupSquash(inst
, stage_num
, tid
);
160 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i] Squashing from "
161 "stage %i. Redirecting fetch to %s.\n", tid
,
162 inst
->seqNum
, stage_num
, pc
);
163 DPRINTF(InOrderStall
, "STALL: [tid:%i]: Branch"
164 " misprediction at %s\n", tid
, inst
->pcState());
166 if (inst
->predTaken()) {
167 predictedTakenIncorrect
++;
168 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
169 "PC %s ... Mispredicts! "
170 "(Prediction: Taken)\n",
172 inst
->staticInst
->disassemble(
176 predictedNotTakenIncorrect
++;
177 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
178 "PC %s ... Mispredicts! "
179 "(Prediction: Not Taken)\n",
181 inst
->staticInst
->disassemble(
185 predictedIncorrect
++;
187 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: Prediction"
188 "Correct.\n", inst
->readTid(), seq_num
);
194 DPRINTF(Fault
, "[tid:%i]:[sn:%i]: Fault %s found\n",
195 inst
->readTid(), inst
->seqNum
, fault
->name());
200 // Regular ALU instruction
201 fault
= inst
->execute();
204 if (fault
== NoFault
) {
207 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: The result "
208 "of execution is 0x%x.\n", inst
->readTid(),
210 (inst
->resultType(0) == InOrderDynInst::Float
) ?
211 inst
->readFloatResult(0) : inst
->readIntResult(0));
213 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: had a %s "
214 "fault.\n", inst
->readTid(), seq_num
, fault
->name());
215 DPRINTF(Fault
, "[tid:%i]:[sn:%i]: Fault %s found\n",
216 inst
->readTid(), inst
->seqNum
, fault
->name());
226 fatal("Unrecognized command to %s", resName
);