src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                              int res_latency, InOrderCPU *_cpu,
  43                              ThePipeline::Params *params)
  44     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  45       lastExecuteTick(0), lastControlTick(0), serializeTick(0)
  46 { }
  47
  48 void
  49 ExecutionUnit::regStats()
  50 {
  51     predictedTakenIncorrect
  52         .name(name() + ".predictedTakenIncorrect")
  53         .desc("Number of Branches Incorrectly Predicted As Taken.");
  54
  55     predictedNotTakenIncorrect
  56         .name(name() + ".predictedNotTakenIncorrect")
  57         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  58
  59     executions
  60         .name(name() + ".executions")
  61         .desc("Number of Instructions Executed.");
  62
  63
  64     predictedIncorrect
  65         .name(name() + ".mispredicted")
  66         .desc("Number of Branches Incorrectly Predicted");
  67
  68     predictedCorrect
  69         .name(name() + ".predicted")
  70         .desc("Number of Branches Incorrectly Predicted");
  71
  72     mispredictPct
  73         .name(name() + ".mispredictPct")
  74         .desc("Percentage of Incorrect Branches Predicts")
  75         .precision(6);
  76     mispredictPct = (predictedIncorrect /
  77                      (predictedCorrect + predictedIncorrect)) * 100;
  78
  79     Resource::regStats();
  80 }
  81
  82 void
  83 ExecutionUnit::execute(int slot_num)
  84 {
  85     ResourceRequest* exec_req = reqs[slot_num];
  86     DynInstPtr inst = reqs[slot_num]->inst;
  87     Fault fault = NoFault;
  88     int seq_num = inst->seqNum;
  89     Tick cur_tick = curTick();
  90
  91     if (cur_tick == serializeTick) {
  92         DPRINTF(InOrderExecute, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
  93                 "All instructions are being serialized this cycle\n",
  94                 inst->readTid(), seq_num, inst->pcState(), inst->instName());
  95         exec_req->done(false);
  96         return;
  97     }
  98
  99
 100     switch (exec_req->cmd)
 101     {
 102       case ExecuteInst:
 103         {
 104             DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 105                     inst->readTid(), seq_num, inst->pcState(), inst->instName());
 106
 107             if (cur_tick != lastExecuteTick) {
 108                 lastExecuteTick = cur_tick;
 109             }
 110
 111             assert(!inst->isMemRef());
 112
 113             if (inst->isSerializeAfter()) {
 114                 serializeTick = cur_tick;
 115                 DPRINTF(InOrderExecute, "Serializing execution after [tid:%i] "
 116                         "[sn:%i] [PC:%s] %s.\n", inst->readTid(), seq_num,
 117                         inst->pcState(), inst->instName());
 118             }
 119
 120             if (inst->isControl()) {
 121                 if (lastControlTick == cur_tick) {
 122                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 123                             "Inst Per Cycle. Blocking Request.\n");
 124                     exec_req->done(false);
 125                     return;
 126                 }
 127                 lastControlTick = curTick();
 128
 129                 // Evaluate Branch
 130                 fault = inst->execute();
 131                 executions++;
 132
 133                 inst->setExecuted();
 134
 135                 if (fault == NoFault) {
 136                     // If branch is mispredicted, then signal squash
 137                     // throughout all stages behind the pipeline stage
 138                     // that got squashed.
 139                     if (inst->mispredicted()) {
 140                         int stage_num = exec_req->getStageNum();
 141                         ThreadID tid = inst->readTid();
 142                         // If it's a branch ...
 143                         if (inst->isDirectCtrl()) {
 144                             assert(!inst->isIndirectCtrl());
 145
 146                             TheISA::PCState pc = inst->pcState();
 147                             TheISA::advancePC(pc, inst->staticInst);
 148                             inst->setPredTarg(pc);
 149
 150                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 151                                 inst->bdelaySeqNum = seq_num;
 152
 153                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 154                                         " branch inst [sn:%i] PC %s mis"
 155                                         "predicted as taken.\n", tid,
 156                                         seq_num, inst->pcState());
 157                             } else if (!inst->predTaken() &&
 158                                        inst->isCondDelaySlot()) {
 159                                 inst->bdelaySeqNum = seq_num;
 160                                 inst->procDelaySlotOnMispred = true;
 161
 162                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 163                                         " branch inst [sn:%i] PC %s mis"
 164                                         "predicted as not taken.\n", tid,
 165                                         seq_num, inst->pcState());
 166                             } else {
 167 #if ISA_HAS_DELAY_SLOT
 168                                 inst->bdelaySeqNum = seq_num + 1;
 169 #else
 170                                 inst->bdelaySeqNum = seq_num;
 171 #endif
 172                                 DPRINTF(InOrderExecute, "[tid:%i]: "
 173                                         "Misprediction detected at "
 174                                         "[sn:%i] PC %s,\n\t squashing after "
 175                                         "delay slot instruction [sn:%i].\n",
 176                                         tid, seq_num, inst->pcState(),
 177                                         inst->bdelaySeqNum);
 178                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 179                                         " misprediction at %s\n",
 180                                         tid, inst->pcState());
 181                             }
 182
 183                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
 184                                     "fetch to %s.\n", tid,
 185                                     inst->readPredTarg());
 186
 187                         } else if (inst->isIndirectCtrl()){
 188                             TheISA::PCState pc = inst->pcState();
 189                             TheISA::advancePC(pc, inst->staticInst);
 190                             inst->seqNum = seq_num;
 191                             inst->setPredTarg(pc);
 192
 193 #if ISA_HAS_DELAY_SLOT
 194                             inst->bdelaySeqNum = seq_num + 1;
 195 #else
 196                             inst->bdelaySeqNum = seq_num;
 197 #endif
 198
 199                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
 200                                     " fetch to %s.\n", tid,
 201                                     inst->readPredTarg());
 202                         } else {
 203                             panic("Non-control instruction (%s) mispredict"
 204                                   "ing?!!", inst->staticInst->getName());
 205                         }
 206
 207                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
 208                                 "start from stage %i.\n", tid, stage_num);
 209
 210                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
 211                                                                          tid);
 212
 213                         inst->squashingStage = stage_num;
 214
 215                         // Squash throughout other resources
 216                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
 217                                                     ResourcePool::SquashAll,
 218                                                     inst, 0, 0, tid);
 219
 220                         if (inst->predTaken()) {
 221                             predictedTakenIncorrect++;
 222                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 223                                     "PC %s ... Mispredicts! (Taken)\n",
 224                                     tid, inst->seqNum,
 225                                     inst->staticInst->disassemble(
 226                                         inst->instAddr()),
 227                                     inst->pcState());
 228                         } else {
 229                             predictedNotTakenIncorrect++;
 230                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 231                                     "PC %s ... Mispredicts! (Not Taken)\n",
 232                                     tid, inst->seqNum,
 233                                     inst->staticInst->disassemble(
 234                                         inst->instAddr()),
 235                                     inst->pcState());
 236                         }
 237                         predictedIncorrect++;
 238                     } else {
 239                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 240                                 "Correct.\n", inst->readTid(), seq_num);
 241                         predictedCorrect++;
 242                     }
 243
 244                     exec_req->done();
 245                 } else {
 246                     warn("inst [sn:%i] had a %s fault",
 247                          seq_num, fault->name());
 248                 }
 249             } else {
 250                 // Regular ALU instruction
 251                 fault = inst->execute();
 252                 executions++;
 253
 254                 if (fault == NoFault) {
 255                     inst->setExecuted();
 256
 257                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
 258                             "of execution is 0x%x.\n", inst->readTid(),
 259                             seq_num,
 260                             (inst->resultType(0) == InOrderDynInst::Float) ?
 261                             inst->readFloatResult(0) : inst->readIntResult(0));
 262                 } else {
 263                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 264                             "fault.\n", inst->readTid(), seq_num, fault->name());
 265                     inst->fault = fault;
 266                 }
 267
 268                 exec_req->done();
 269             }
 270         }
 271         break;
 272
 273       default:
 274         fatal("Unrecognized command to %s", resName);
 275     }
 276 }
 277
 278