src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                              int res_latency, InOrderCPU *_cpu,
  43                              ThePipeline::Params *params)
  44     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  45       lastExecuteTick(0), lastControlTick(0)
  46 { }
  47
  48 void
  49 ExecutionUnit::regStats()
  50 {
  51     predictedTakenIncorrect
  52         .name(name() + ".predictedTakenIncorrect")
  53         .desc("Number of Branches Incorrectly Predicted As Taken.");
  54
  55     predictedNotTakenIncorrect
  56         .name(name() + ".predictedNotTakenIncorrect")
  57         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  58
  59     executions
  60         .name(name() + ".executions")
  61         .desc("Number of Instructions Executed.");
  62
  63
  64     predictedIncorrect
  65         .name(name() + ".mispredicted")
  66         .desc("Number of Branches Incorrectly Predicted");
  67
  68     predictedCorrect
  69         .name(name() + ".predicted")
  70         .desc("Number of Branches Incorrectly Predicted");
  71
  72     mispredictPct
  73         .name(name() + ".mispredictPct")
  74         .desc("Percentage of Incorrect Branches Predicts")
  75         .precision(6);
  76     mispredictPct = (predictedIncorrect /
  77                      (predictedCorrect + predictedIncorrect)) * 100;
  78
  79     Resource::regStats();
  80 }
  81
  82 void
  83 ExecutionUnit::execute(int slot_num)
  84 {
  85     ResourceRequest* exec_req = reqMap[slot_num];
  86     DynInstPtr inst = reqMap[slot_num]->inst;
  87     Fault fault = reqMap[slot_num]->fault;
  88     ThreadID tid = inst->readTid();
  89     int seq_num = inst->seqNum;
  90
  91     exec_req->fault = NoFault;
  92
  93     DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
  94             tid, seq_num, inst->pcState(), inst->instName());
  95
  96     switch (exec_req->cmd)
  97     {
  98       case ExecuteInst:
  99         {
 100             if (curTick() != lastExecuteTick) {
 101                 lastExecuteTick = curTick();
 102             }
 103
 104
 105             if (inst->isMemRef()) {
 106                 panic("%s not configured to handle memory ops.\n", resName);
 107             } else if (inst->isControl()) {
 108                 if (lastControlTick == curTick()) {
 109                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 110                             "Inst Per Cycle. Blocking Request.\n");
 111                     exec_req->done(false);
 112                     return;
 113                 }
 114                 lastControlTick = curTick();
 115
 116                 // Evaluate Branch
 117                 fault = inst->execute();
 118                 executions++;
 119
 120                 inst->setExecuted();
 121
 122                 if (fault == NoFault) {
 123                     // If branch is mispredicted, then signal squash
 124                     // throughout all stages behind the pipeline stage
 125                     // that got squashed.
 126                     if (inst->mispredicted()) {
 127                         int stage_num = exec_req->getStageNum();
 128                         ThreadID tid = inst->readTid();
 129
 130                         // If it's a branch ...
 131                         if (inst->isDirectCtrl()) {
 132                             assert(!inst->isIndirectCtrl());
 133
 134                             TheISA::PCState pc = inst->pcState();
 135                             TheISA::advancePC(pc, inst->staticInst);
 136                             inst->setPredTarg(pc);
 137
 138                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 139                                 inst->bdelaySeqNum = seq_num;
 140
 141                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 142                                         " branch inst [sn:%i] PC %s mis"
 143                                         "predicted as taken.\n", tid,
 144                                         seq_num, inst->pcState());
 145                             } else if (!inst->predTaken() &&
 146                                        inst->isCondDelaySlot()) {
 147                                 inst->bdelaySeqNum = seq_num;
 148                                 inst->procDelaySlotOnMispred = true;
 149
 150                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 151                                         " branch inst [sn:%i] PC %s mis"
 152                                         "predicted as not taken.\n", tid,
 153                                         seq_num, inst->pcState());
 154                             } else {
 155 #if ISA_HAS_DELAY_SLOT
 156                                 inst->bdelaySeqNum = seq_num + 1;
 157 #else
 158                                 inst->bdelaySeqNum = seq_num;
 159 #endif
 160                                 DPRINTF(InOrderExecute, "[tid:%i]: "
 161                                         "Misprediction detected at "
 162                                         "[sn:%i] PC %s,\n\t squashing after "
 163                                         "delay slot instruction [sn:%i].\n",
 164                                         tid, seq_num, inst->pcState(),
 165                                         inst->bdelaySeqNum);
 166                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 167                                         " misprediction at %s\n",
 168                                         tid, inst->pcState());
 169                             }
 170
 171                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
 172                                     "fetch to %s.\n", tid,
 173                                     inst->readPredTarg());
 174
 175                         } else if (inst->isIndirectCtrl()){
 176                             TheISA::PCState pc = inst->pcState();
 177                             TheISA::advancePC(pc, inst->staticInst);
 178                             inst->seqNum = seq_num;
 179                             inst->setPredTarg(pc);
 180
 181 #if ISA_HAS_DELAY_SLOT
 182                             inst->bdelaySeqNum = seq_num + 1;
 183 #else
 184                             inst->bdelaySeqNum = seq_num;
 185 #endif
 186
 187                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
 188                                     " fetch to %s.\n", tid,
 189                                     inst->readPredTarg());
 190                         } else {
 191                             panic("Non-control instruction (%s) mispredict"
 192                                   "ing?!!", inst->staticInst->getName());
 193                         }
 194
 195                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
 196                                 "start from stage %i.\n", tid, stage_num);
 197
 198                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
 199                                                                          tid);
 200
 201                         inst->squashingStage = stage_num;
 202
 203                         // Squash throughout other resources
 204                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
 205                                                     ResourcePool::SquashAll,
 206                                                     inst, 0, 0, tid);
 207
 208                         if (inst->predTaken()) {
 209                             predictedTakenIncorrect++;
 210                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 211                                     "PC %s ... Mispredicts! (Taken)\n",
 212                                     tid, inst->seqNum,
 213                                     inst->staticInst->disassemble(
 214                                         inst->instAddr()),
 215                                     inst->pcState());
 216                         } else {
 217                             predictedNotTakenIncorrect++;
 218                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 219                                     "PC %s ... Mispredicts! (Not Taken)\n",
 220                                     tid, inst->seqNum,
 221                                     inst->staticInst->disassemble(
 222                                         inst->instAddr()),
 223                                     inst->pcState());
 224                         }
 225                         predictedIncorrect++;
 226                     } else {
 227                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 228                                 "Correct.\n", inst->readTid(), seq_num);
 229                         predictedCorrect++;
 230                     }
 231
 232                     exec_req->done();
 233                 } else {
 234                     warn("inst [sn:%i] had a %s fault",
 235                          seq_num, fault->name());
 236                 }
 237             } else {
 238                 // Regular ALU instruction
 239                 fault = inst->execute();
 240                 executions++;
 241
 242                 if (fault == NoFault) {
 243                     inst->setExecuted();
 244
 245                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
 246                             "of execution is 0x%x.\n", inst->readTid(),
 247                             seq_num,
 248                             (inst->resultType(0) == InOrderDynInst::Float) ?
 249                             inst->readFloatResult(0) : inst->readIntResult(0));
 250
 251                     exec_req->done();
 252                 } else {
 253                     warn("inst [sn:%i] had a %s fault",
 254                          seq_num, fault->name());
 255                     cpu->trap(fault, tid, inst);
 256                 }
 257             }
 258         }
 259         break;
 260
 261       default:
 262         fatal("Unrecognized command to %s", resName);
 263     }
 264 }
 265
 266